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AN-1026: DescriptionMaximum Power Enhancement Techniques for SuperSOTTM-6 Power MOSFETs; File Size233KB，13 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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Maximum Power Enhancement Techniques for SuperSOTTM-6 Power MOSFETs

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AN1026

April, 1996

Maximum Power Enhancement Techniques for SuperSOT

-6 Power

MOSFETs

Alan Li, Brij Mohan, Steve Sapp, Izak Bencuya, Linh Hong

1. Introduction

As packages become smaller, achieving efficient thermal performance for power applications re-

quires that the designers employ new methods of meliorating the heat flow out of devices. Thus

the purpose of this paper is to aid the user in maximizing the power handling capability of the

SuperSOT

-6 Power MOSFET offered by Fairchild Semiconductor. This effort allows the user to

take full advantage of the exceptional performance features of Fairchild’s state-of-the-art Power

MOSFET which offers very low on-resistance and improved junction-to-case (R

θJC

)

thermal resis-

tance. Ultimately the user may achieve improved component performance and higher circuit board

packing density by using the thermal solution suggested below.

In natural cooling, the method of improving power performance should be focused on the optimum

design of copper mounting pads. The design should take into consideration the size of the copper

and its placement on either or both of the board surfaces. A copper mounting pad is important

because the drain leads of the Power MOSFET are mounted directly onto the pad. The pad acts

as a heatsink to reduce thermal resistance and leads to improved power performance.

Figure 1. SuperSOT

-6 Power MOSFET achieves junction-to-case thermal resistance R

θJC

of 30

C/W

for single device and 60

C/W for dual devices.

2. Theory

When a device operates in a system under the steady-state condition, the maximum power

dissipation is determined by the maximum junction temperature rating, the ambient temperature,

and the junction-to-ambient thermal resistance.

Dmax

= ( T

Jmax

- T

) / R

θJA

(2.1)

The term junction refers to the point of thermal reference of the semiconductor. Equation 2.1 can

also be applied to the transient-state:

Dmax

(t) = [ T

Jmax

- T

] / R

θJA

(t) (2.2)

Rev B, August 1998

where P

Dmax

(t) and R

θJA

(t) are time dependent. By using the transient thermal resistance curves

shown in the data sheet, a transient temperature change can be calculated. The transient thermal

behavior is a complicated subject because R

θJA

(t) increases non-linearly with time and the condi-

tions of the power pulse. A more thorough treatment of transient power analysis is beyond the

scope of this document and the reader can refer to [13] for details. Nevertheless, Fairchild provides

a Discrete SPICE Thermal Model (LIT# 570240-002) for general thermal evaluation. User may find

these models helpful in determining the dynamic power and temperature limits in the application.

θJA

has two distinct elements, R

θJC

junction-to-case and R

θCA

case-to-ambient thermal resistance.

θJA

θJC

θCA

(2.3)

The case thermal reference of the SuperSOT

-6 Power MOSFET is defined as the point of con-

tact between the drain leads of the package and the mounting surface.

θCA

is influenced by many variables such as ambient temperature, board layout, and cooling

method. Due to the lack of an industry standard, the value of R

θCA

is not easily defined and can

affect

θJA

significantly. In addition, the case reference may be defined differently by various manu-

facturers. Under such conditions, it becomes difficult to define R

θCA

from the component manufac-

turer standpoint. On the other hand, R

θJC

is independent of users’ conditions and can be accu-

rately measured by the component manufacturer.

Therefore, in this paper an effort has been made to define a procedure which can be used to

quantify the junction-to-ambient thermal resistance R

θJA

which is more useful to the circuit board

designer.

3. Result

The scope of the investigation has been limited to the size of copper mounting pad and its relative

surface placement on the board. In still air with no heatsink, the application of these heat dissipa-

tion methods is the most cost effective thermal solution. A total of sixteen different combinations

of 2 Oz copper pad sizes and their placement were designed to study their influence on R

θJA

thermal resistance. The configurations of the board layout are shown in figure 2 and table 1. For

single device, layouts 1 to 6 have the copper pad sizes from 0.003 to 0.4 square inches on the top

side of the board (top side is defined as the component side of the board). Layouts 7 to 11 have

copper pad sizes from 0.03 to 0.4 square inches on the bottom side of the board. Layouts 12 to

16 have copper pad sizes from 0.02 to 0.4 square inches divided equally on both sides of the

board. For dual devices, layouts 1, 2, and 5 have copper sizes from 0.0015 to 0.125 square inches

on the top side of the board.

BOTTEM VIEW

SOT-6 THERMAL BOARD

TOP VIEW

Figure 2. Both Sides of the 4.5”x5”

SuperSOT

-6 Thermal Board. Complete

scale drawings are shown in Section 5.

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