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AN-6754A
Design Guideline to Replace SG6742 with FAN6754A
Introduction
FAN6754A is a highly integrated PWM controller featuring
green mode, frequency hopping, constant power limit, and a
number of protection functions. The green-mode function,
burst-mode function, and a low operating current maximize
the light-load efficiency so that the power supply can meet
stringent standby power regulations. Frequency hopping
reduces the Electro-Magnetic Emission (EMI) by spreading
the frequency spectrum. The constant-power-limit function
minimizes the component stress in abnormal conditions and
helps optimize the power stage design. Protection functions
such as brownout protection, overload / open-loop
protection (OLP), over-voltage protection (OVP), sense pin
short-circuit protection (SSCP), and over-temperature
protection (OTP) are fully integrated to improve the
reliability of the switched-mode power supply without
Table 1.
Comparison of SG6742 and FAN6754A
SG6742
Brownout Protection
Line Voltage Compensation for Pulse-by-
Pulse Current Limit (V
Limit-L
/ V
Limit-H
)
Sense Pin Short-Circuit Protection
Gate Drive Clamping Voltage
FB Impedance (Z
FB
)
Operating Current (I
DD_OP
)
Leading-Edge Blanking Time (t
LEB
)
Soft-Start
Maximum Duty Cycle
V
FB-G
/V
FB-N
for Green Mode
V
ZDC
/V
ZDCR
for Burst Mode
V
No
Saw-Limit (0.9V / 0.56V)
SENSE
increasing system cost. This application note explains how
to replace PWM controller SG6742 with FAN6754A. These
two devices have the same pin configuration and direct
replacement can be achieved without PCB layout change.
However, functional improvements to the FAN6754A for
higher efficiency and better performance requires several
external components to be changed accordingly. Table 1
summarizes the difference between these two devices. The
pulse-by-pulse current limit threshold voltage is reduced
almost by half to reduce the current sensing loss, which
results in 0.4~0.5% efficiency improvement. The operating
current is also reduced to achieve less than 100mW standby
power consumption for most designs. The typical
application circuit and internal block diagram are shown in
Figure 1 and Figure 2 , respectively.
FAN6754A
Line Sensing Using HV Pin
Adjusted by HV Pin (0.46V / 0.39V)
V
SENSE
<0.15V Longer than 150µs
18V
5KΩ
2.7mA
150ns
5ms
65%
2.4V / 3.0V
1.6V / 1.7V
<0.05V Longer than 120µs
13V
15.5KΩ
1.7mA
280ns
8ms
89%
2.3V / 2.8V
2.0V / 2.1V
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/10
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AN-6754A
APPLICATION NOTE
Figure 1.
Typical Application
Figure 2.
Internal Block Diagram
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/10
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AN-6754A
APPLICATION NOTE
HV Startup Circuit
Figure 3 shows the simplified schematic for the HV startup
circuit. When the AC line is applied to the power supply, the
internal high-voltage current source charges the hold-up
capacitor C
1
through startup resistor R
HV
. As the V
DD
pin
voltage reaches the turn-on threshold V
DD-ON
, the PWM
controller is enabled and starts normal operation. Then the
high-voltage current source is switched off and the supply
current is drawn from the auxiliary winding of the main
transformer, as shown in Figure 3. For better line surge
immunity on the HV pin, it is typical to use a HV resistor
larger than 150kΩ. When a large C1 capacitor is required
for V
DD
, the HV resistor limits the charging current for the
V
DD
capacitor, increasing the startup time. If a shorter
startup time is required, a two-stage V
DD
capacitor circuit,
shown in Figure 3, is recommended.
Under-Voltage Lockout (UVLO)
The FAN6754A has an under-voltage lockout for V
DD
.
Figure 5 shows the turn-on (V
DD-ON
) and turn-off (V
DD-OFF
)
threshold levels. Note that there is another V
DD
turn-off level
(V
DD-OLP
) to minimize the power dissipation of the power
stage during the overload protection / open-loop protection
condition by extending the V
DD
discharge time.
If the output short is overloaded or the feedback loop is
opened, the FB voltage remains above V
FB-OLP
for OLP
delay time (t
D-OLP
) until the protection is triggered. During
that time, the MOSFET drain-to-source current reaches its
pulse-by-pulse current limit level for every switching cycle,
causing a large amount of power dissipation to the switching
devices and transformer. With the two-step UVLO
mechanism, the average input power during overload or
open-loop condition is significantly reduced.
Figure 3.
Startup Circuit
Soft-Start
The FAN6754A has an internal soft-start circuit that
progressively increases the pulse-by-pulse current limit level
as shown in Figure 4. The built-in soft-start circuit
significantly reduces the input current overshoot during
startup, which also minimizes output voltage overshoot.
V
DD-ON
Figure 5.
UVLO Specification
V
DD
V
DD-OFF
General
UVLO
Gate
V
LIMIT
(V)
0.46
V
DD-ON
0.4
0.36
0.28
V
DD
V
DD-OFF
V
DD-OLP
Two-Step
UVLO
Gate
0.2
Figure 6.
0.1
1
3
4
5
7
Two-Level UVLO
time (ms)
Figure 4.
Pulse-by-Pulse Current Limit Level
for Soft-Start
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© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/10
AN-6754A
APPLICATION NOTE
Green-Mode Operation
The FAN6754A uses feedback voltage (V
FB
) as an indicator
of the output load and modulates the PWM frequency, as
shown in Figure 7, such that the switching frequency
decreases as load decreases. In heavy-load conditions, the
switching frequency is 65KHz. Once V
FB
decreases below
V
FB-N
(2.8V), the PWM frequency starts to linearly decrease
from 65KHz to 22kHz to reduce the switching losses. As
V
FB
decreases below V
FB-G
(2.3V), the switching frequency
is fixed at 22kHz. As V
FB
decreases below V
FB-ZDC
(2.0V),
the FAN6754A enters burst-mode operation. When V
FB
drops below V
FB-ZDC
, the FAN6754A stops switching and
the output voltage starts to drop, which causes the feedback
voltage to rise. Once V
FB
rises above V
FB-ZDCR
, switching
resumes. Burst mode alternately enables and disables
switching, thereby reducing switching loss in standby mode,
as shown in Figure 8.
FB Input
The FAN6754A employs peak-current-mode control as
shown in Figure 9. A current-to-voltage conversion is
accomplished externally with current-sense resistor R
CS
.
Figure 9.
Synchronized Slope Compensation
Figure 7.
Frequency Modulation
Figure 10 is a typical feedback circuit mainly consisting of a
shunt regulator and an opto-coupler. R1 and R2 form a
voltage divider for output voltage regulation. R3 and C1 are
adjusted for control-loop compensation. A small-value RC
filter (e.g. R
FB
=10Ω, C
FB
=1nF) placed between the FB pin
and GND pin can increase loop stability substantially. The
maximum source current of the FB pin is about 330μA (FB
through 15kΩ pulled to 5V reference internally). The
phototransistor must be capable of sinking this current to
pull the FB level down at no-load condition. Rb and the
internal FB pull-up resistor determines the gain feedback
loop. The internal pull-up resistor in the SG6742 is 5kΩ,
but the FAN6754A has a larger pull-up resistor (15kΩ) to
reduce power consumption. Therefore, Rb should be three
times the original value when a SG6742 design is replaced
with the FAN6754A to have the same loop gain.
Forcing FB by an external voltage is not recommended.
Figure 10.
Feedback Circuit
Figure 8.
Burst Mode
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/10
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AN-6754A
APPLICATION NOTE
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs across the sense-resistor, R
S
in Figure 11,
caused by primary-side capacitance and secondary-side
rectifier reverse recovery. To avoid premature termination
of the switching pulse, a leading-edge blanking time is built
in. During this blanking period (280ns), the PWM
comparator is disabled and cannot switch off the gate driver.
Thus, RC filter with a small RC time constant (e.g. 100Ω +
470pF) is enough for current sensing. A non-inductive
resistor for R
S
is recommended.
as line voltage increases to makes the actual power limit
level almost constant over different line voltages within a
universal input voltage range, as shown in Figure 13. In the
FAN6754A, the peak-current limiting threshold is adjusted
by the peak voltage of the HV pin. When the internal circuit
detailed in Figure 14 samples the line voltage information,
an internal 1.62kΩ resistor is connected to the HV pin to
scale down the line voltage by forming a voltage divider
with resistor R
HV
and the internal resistor.
Figure 13.
Universal Line Voltage Compensation
for Constant Output Power Limit
AC In
V
Limit
(V)
R
HV
0.46
V
IN
0.39
Figure 11.
Turn-On Spike
1.62kΩ
GND
Output Driver / Soft Driving
The output stage is a fast totem-pole gate driver capable of
directly driving external MOSFETs. An internal Zener
diode, shown in Figure 12, clamps the driver voltage under
13V to protect the MOSFET gate from over voltage. With
integrating circuits to control the slew rate of the switch
turn-on rise time, the external resistor R
G
may not be
necessary to reduce switching noise.
V
DD
On/Off
Logic
Line Sample
Circuit
V
IN
(V)
1V
3V
Figure 14.
HV Sampling Circuit and V
Limit
Level
vs. V
IN
Brownout Protection in HV Pin
As shown in Figure 15, the AC line voltage is monitored by
the HV pin using a resistor (R
HV
), a diode (D
1
), and an
internal line voltage sample circuit. Figure 16 shows
brownout protection behavior when the circuit uses the half-
wave of the AC line input (V
HV
) at the HV pin. When the
V
HV
is larger than the brown-in detection voltage threshold
(V
AC-ON
) and V
DD
is higher than V
DD-AC
, the PWM begins to
operate without any debounce time. Meanwhile, the PWM
stops operating when V
HV
is less than the detection voltage
threshold (V
AC-OFF
) for longer than debounce time.
The V
AC-ON
and V
AC-OFF
are calculated using the following
equations:
V
AC-ON
(
RMS
)
=
(0.9
×
V
AC -OFF
(RMS)
=
(0.81
×
13V
R
G
Gate
R
S
FAN6754A
Figure 12.
Gate Driver
High/Low Line Compensation in HV Pin
The conventional pulse-by-pulse current limiting scheme
has a constant threshold for the current-limit comparator,
which results in a higher power limit for high line voltage.
The FAN6754A has a current-limit threshold that decreases
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/10
5
R
HV
+
1.6
)/ 2
1.6
(1)
(2)
R
HV
+
1.6
) / 2
or where R
HV
is in k
Ω
.
1.6
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