FAN3278 — 30V PMOS-NMOS Bridge Driver
January 2011
FAN3278
30V PMOS-NMOS Bridge Driver
Features
8V to 27V Optimum Operating Range
Drives High-Side PMOS and Low-Side NMOS in
Motor Control or Buck Step-Down Applications
Output Drive-Voltage Magnitude Limited: < 13V
for V
DD
up to 30V
Biases Each Load Device OFF with a 100kΩ
Resistor when V
DD
Below Operating Level
Low-Voltage TTL Input Thresholds
Peak Gate Drives at 12V: +1.5A Sink, -1.0A Source
Internal Resistors Hold Driver Off When
No Inputs Present
8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Description
The FAN3278 dual 1.5A gate driver is optimized to drive
a high-side P-channel MOSFET and a low-side
N-channel MOSFET in motor control applications
operating from a voltage rail up to 27V. Internal circuitry
limits the voltage applied to the gates of the external
MOSFETs to 13V maximum. The driver has TTL input
thresholds and provides buffer and level translation from
logic inputs. Internal circuitry prevents the output
switching devices from operating if the V
DD
supply
voltage is below the IC operation level. Internal 100kΩ
resistors bias the non-inverting output LOW and the
inverting output to V
DD
to keep the external MOSFETs
off during startup intervals when logic control signals
may not be present.
The FAN3278 driver incorporates MOSFET devices for
the final output stage, providing high current throughout
the MOSFET turn-on / turn-off transition to minimize
switching loss. The internal gate-drive regulators
provide optimum gate-drive voltage when operating
from a rail of 8V to 27V. The FAN3278 can be driven
from a voltage rail of less than 8V; however, its gate
drive current is reduced.
The FAN3278 has two independent ENABLE pins that
default to ON if not connected. If the ENABLE pin for
non-inverting channel A is pulled LOW, OUTA is forced
LOW. If the ENABLE pin for inverting channel B is
pulled LOW, OUTB is forced HIGH. If an input is left
unconnected, internal resistors bias the inputs such that
the external MOSFETs are OFF.
Applications
Motor Control with PMOS / NMOS Half-Bridge
Configuration
Buck Converters with High-Side PMOS Device;
100% Duty Cycle Operation Possible
Logic-Controlled Load Circuits with High-Side
PMOS Switch
Figure 1. Typical Application
© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
www.fairchildsemi.com
FAN3278 — 30V PMOS-NMOS Bridge Driver
Ordering Information
Part Number
FAN3278TMX
Logic
Non-Inverting Channel and Inverting Channel with Dual Enable
Input
Threshold
TTL
Packing
Method
2,500 Units on
Tape & Reel
Figure 2. Typical 3-Phase Blower Motor Drive Application
© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
www.fairchildsemi.com
2
FAN3278 — 30V PMOS-NMOS Bridge Driver
Pin Configuration
Figure 3. Pin Configuration (Top View)
Thermal Characteristics
(1)
Package
8-Pin Small-Outline Integrated Circuit (SOIC)
JL(2)
40
JT(3)
31
JA(4)
89
JB(5)
43
JT(6)
3
Unit
°C/W
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (
JL
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
3. Theta_JT (
JT
): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (Θ
JA
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB (
JB
): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 4. For
the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (
JT
): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.
Pin Definitions
Pin#
1
8
3
2
4
7
5
6
Name
ENA
ENB
GND
INA
INB
OUTA
OUTB
Description
Enable Input for Channel A.
Pull pin LOW to inhibit driver A. ENA has TTL thresholds.
Enable Input for Channel B.
Pull pin LOW to inhibit driver B. ENB has TTL thresholds.
Ground.
Common ground reference for input and output circuits.
Input to Channel A.
Input to Channel B.
Gate Drive Output A:
Held LOW unless required input is present and V
DD
is above the internal
voltage threshold where the IC is functional.
Gate Drive Output B
(inverted from the input). Held HIGH unless the required input is present
and V
DD
is above the internal voltage threshold where the IC is functional.
Supply Voltage.
Provides power to the IC.
VDD
© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
www.fairchildsemi.com
3
FAN3278 — 30V PMOS-NMOS Bridge Driver
Output Logic
FAN3278 (Channel A)
ENA
0
0
1
1
(7)
(7)
FAN3278 (Channel B)
OUTA
0
0
0
1
ENB
0
0
1
1
(7)
(7)
INA
0
(7)
1
0
(7)
INB
0
(7)
1
0
(7)
OUTB
1
1
1
0
1
1
Note:
7. Default input signal if no external connection is made.
Block Diagram
V
DD
100k
V
DD
100k
ENA
1
13V
8
ENB
INA
2
100k
LS
Predriver
100k
7
OUTA
Low-Side
Drive
Regulator
GND
3
6
VDD
High-Side
Drive
Regulator
HS
Predriver
100k
INB
4
100k
5
OUTB
V
DD
- 13V
Figure 4. Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
www.fairchildsemi.com
4
FAN3278 — 30V PMOS-NMOS Bridge Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
EN
V
IN
V
OUT
T
L
T
J
T
STG
ESD
VDD to PGND
ENA, ENB to GND
INA, INB to GND
OUTA, OUTB to GND
Parameter
Min.
-0.3
Max.
30.0
Unit
V
V
V
V
ºC
ºC
ºC
kV
GND - 0.3 V
DD
+ 0.3
GND - 0.3 V
DD
+ 0.3
GND - 0.3 V
DD
+ 0.3
+260
-55
-65
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101
2
2
+150
+150
Lead Soldering Temperature (10 Seconds)
Junction Temperature
Storage Temperature
Electrostatic Discharge
Protection Level
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
DD
V
EN
V
IN
T
A
Supply Voltage Range
Enable Voltage (ENA, ENB)
Input Voltage (INA, INB)
Parameter
Min.
8
0
0
-40
Max.
27
V
DD
V
DD
+125
Unit
V
V
V
°C
Operating Ambient Temperature
© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
www.fairchildsemi.com
5
京公网安备 11010802033920号
EEWORLD
