IBM25PPC405EP-3GA266CZ datasheet, PDF

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IBM25PPC405EP-3GA266CZ: DescriptionRISC Microprocessor, 32-Bit, 266.66MHz, CMOS, PBGA385, 31 X 31 MM, ENHANCED, PLASTIC, BGA-385; CategoryThe embedded processor and controller Microcontrollers and processors; File Size523KB，52 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM25PPC405EP-3GA266CZ Overview

RISC Microprocessor, 32-Bit, 266.66MHz, CMOS, PBGA385, 31 X 31 MM, ENHANCED, PLASTIC, BGA-385

IBM25PPC405EP-3GA266CZ Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	BGA
package instruction	BGA, BGA385,23X23,50
Contacts	385
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	REQUIRES 3.3V I/O SUPPLY
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B385
length	31 mm
low power mode	YES
Number of terminals	385
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA385,23X23,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
speed	266.66 MHz
Maximum supply voltage	1.95 V
Minimum supply voltage	1.65 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	31 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Preliminary

PowerPC 405EP Embedded Processor Data Sheet

Features

• IBM PowerPC



405 32-bit RISC processor core

operating up to 266MHz with 16KB D- and I-

caches

• PC-133 synchronous DRAM (SDRAM) interface

- 32-bit interface for non-ECC applications

• 4KB on-chip memory (OCM)

• Programmable timers

• External peripheral bus

- Flash ROM/Boot ROM interface

- Direct support for 8- or 16-bit SRAM and

external peripherals

- Up to five devices

• DMA support for memory and UARTs.

- Scatter-gather chaining supported

- Four channels

• PCI Revision 2.2 compliant interface (32-bit, up

to 66MHz)

- Asynchronous PCI Bus interface

• Software accessible event counters

• Two serial ports (16750 compatible UART)

• One IIC interface

• General purpose I/O (GPIO) available

• Supports JTAG for board level testing

• Internal processor local Bus (PLB) runs at

SDRAM interface frequency

• Supports PowerPC processor boot from PCI

memory

- Internal or external PCI Bus Arbiter

• Two Ethernet 10/100Mbps (full-duplex) ports

with media independent interface (MII)

• Programmable interrupt controller supports

seven external and 19 internal edge triggered or

level-sensitive interrupts

Description

Designed specifically to address embedded

applications, the PowerPC 405EP (PPC405EP)

provides a high-performance, low-power solution

that interfaces to a wide range of peripherals by

incorporating on-chip power management features

and lower power dissipation requirements.

This chip contains a high-performance RISC

processor core, SDRAM controller, PCI bus

interface, Ethernet interface, control for external

ROM and peripherals, DMA with scatter-gather

support, serial ports, IIC interface, and general

purpose I/O.

Technology: IBM CMOS SA-27E, 0.18

(0.11

m L

eff

)

Package: 31mm, 385-ball, enhanced plastic ball

grid array (E-PBGA)

Power (typical): 1.2W at 200MHz

3/19/03

While the information contained herein is believed to be accurate, such information is preliminary, and should not be

relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.

Preliminary

PowerPC 405EP Embedded Processor Data Sheet

Contents

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Tables

System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

I/O Specifications—Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

I/O Specifications—Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3/19/03

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