FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator
May 2010
FAN5355
1A / 0.8A, 3MHz Digitally Programmable Regulator
Features
93% Efficiency at 3MHz
800mA or 1A Output Current
I C™-Compatible Interface up to 3.4Mbps
6-bit V
OUT
Programmable from 0.75V to 1.975V
2.7V to 5.5V Input Voltage Range
3MHz Fixed-Frequency Operation
Excellent Load and Line Transient Response
Small Size, 1μH Inductor Solution
±2% PWM DC Voltage Accuracy
35ns Minimum On-Time
High-Efficiency, Low-Ripple, Light-Load PFM
Smooth Transition between PWM and PFM
37μA Operating PFM Quiescent Current
Pin-Selectable or I C™ Programmable Output Voltage
On-the-Fly External Clock Synchronization
10-lead MLP (3 x 3mm) or 12-bump CSP Packages
2
2
Description
The FAN5355 device is a high-frequency, ultra-fast transient
response, synchronous step-down DC-DC converter
optimized for low-power applications using small, low-cost
inductors and capacitors. The FAN5355 supports up to
800mA or 1A load current.
The device is ideal for mobile phones and similar portable
applications powered by a single-cell Lithium-Ion battery. With
2
an output-voltage range adjustable via I C™ interface from
0.75V to 1.975V, the device supports low-voltage DSPs and
processors, core power supplies, and memory modules in
smart phones, PDAs, and handheld computers.
The FAN5355 operates at 3MHz (nominal) fixed switching
frequency using either its internal oscillator or external SYNC
frequency.
During light-load conditions, the regulator includes a PFM
mode to enhance light-load efficiency. The regulator
transitions smoothly between PWM and PFM modes with no
In hardware shutdown, the current
glitches on V
OUT
.
consumption is reduced to less than 200nA.
The serial interface is compatible with Fast/Standard and
2
High-Speed mode I C specifications, allowing transfers up to
3.4Mbps. This interface is used for dynamic voltage scaling
with 12.5mV voltage steps for reprogramming the mode of
operation (PFM or Forced PWM), or to disable/enable the
output voltage.
The chip's advanced protection features include short-circuit
protection and current and temperature limits. During a
sustained over-current event, the IC shuts down and restarts
after a delay to reduce average power dissipation into a fault.
During startup, the IC controls the output slew rate to minimize
input current and output overshoot at the end of soft start. The
IC maintains a consistent soft-start ramp, regardless of output
load during startup.
The FAN5355 is available in 10-lead MLP (3x3mm) and
12-bump CSP packages.
Applications
Cell Phones, Smart Phones
3G, WiFi , WiMAX™, and WiBro Data Cards
Netbooks , Ultra-Mobile PCs
SmartReflex™-Compliant Power Supply
Split Supply DSPs and
μP
Solutions OMAP™, XSCALE™
Mobile Graphic Processors (NVIDIA , ATI)
LPDDR2 and Memory Modules
®
®
®
®
I
2
C is a trademark of Philips Corporation.
Wi-Fi® is a registered trademark of Wi-Fi Alliance Corporation.
WiMax™ is a trademark of WIMAX Forum Corporation.
WiBro® is a registered trademark of Telecommunications Technology Association.
Netbooks® is a registered trademark of Netbooks, Inc.
SmartReflex and OMAP are trademarks of Texas Instruments.
XSCALE is a trademark of Intel Corporation.
NVIDIA is a registered trademark of NVIDIA Corporation.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.6
www.fairchildsemi.com
FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator
Ordering Information
Slave Address
LSB
Order Number
(1)
Output
Current
mA
800
800
800
1000
1000
V
OUT
Programming
Min.
0.7500
0.7500
0.7500
0.7500
1.1875
Max.
1.5375
1.5375
1.4375
1.5375
1.9750
(2)
Power-up
Defaults
VSEL0 VSEL1 Package
1.05
1.05
1.05
1.00
1.80
1.35
1.35
1.20
1.20
1.80
WLCSP-12, 2.23x1.46mm
MLP-10, 3x3mm
WLCSP-12, 2.23x1.46mm
WLCSP-12, 2.23x1.46mm
WLCSP-12, 2.23x1.46mm
Option
00
00
02
03
06
A1
0
0
1
0
0
A0
0
0
0
0
0
FAN5355UC00X
FAN5355MP00X
FAN5355UC02X
FAN5355UC03X
FAN5355UC06X
Notes:
1. The “X” designator specifies tape and reel packaging.
2.
V
OUT
is limited to the maximum voltage for all VSEL codes
greater than the maximum V
OUT
listed.
Typical Application
AVIN
Q1
PVIN
C
IN
VIN
EN
VSEL
SYNC
VCCIO
SW
VOUT
L
OUT
C
OUT
PGND
VOUT
MODULATOR
SDA
SCL
AGND
Q2
Figure 1. Typical Application
Component
L1 (L
OUT
)
C
OUT
C
IN
Description
1μH nominal
0603
(1.
6x0.8x0.8)
10μF X5R or better
0603 (1.6x0.8x0.8)
4.7μF X5R or better
Vendor
Murata LQM31P
or FDK MIPSA2520
Murata or equivalent
GRM188R60G106ME47D
Murata or equivalent
GRM188R60J475KE19D
Parameter
L
(3)
DCR (series R)
C
(4)
C
(4)
Min.
0.7
Typ.
1.0
100
Max.
1.2
Units
μH
mΩ
5.6
3.0
10.0
4.7
12.0
5.6
μF
μF
Table 1. Recommended External Components
Notes:
3. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases with increasing current).
4. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to
frequency, dielectric, and voltage bias effects.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.6
2
www.fairchildsemi.com
FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator
Pin Configuration
Top View
Bottom View
Top View
Figure 3. MLP10, 3x3mm
Figure 2. WLCSP-12, 2.23x1.46mm
Pin Definitions
Pin #
WLCSP
A1, B1
A2
A3
MLP
9
10
1
Name
(5)
Description
Power GND.
Power return for gate drive and power transistors. Connect to AGND on PCB. The
connection from this pin to the bottom of C
IN
should be as short as possible.
Switching Node.
Connect to output inductor.
Power Input Voltage.
Connect to input power source. The connection from this pin to C
IN
should be as
short as possible.
Sync.
When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin.
In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the
specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock.
Analog Input Voltage.
Connect to input power source as close as possible to the input bypass
capacitor.
Analog GND.
This is the signal ground reference for the IC. All voltage levels are measured with respect
to this pin.
Enable.
When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This
pin should not be left floating.
SDA.
I
2
C interface serial data.
Output Voltage Monitor.
Tie this pin to the output voltage. This is a signal input pin to the control circuit
and does not carry DC current.
Voltage Select.
When HIGH, V
OUT
is set by VSEL1. When LOW, V
OUT
is set by VSEL0. This behavior
can be overridden through I
2
C register settings. This pin should not be left floating.
SCL.
I
2
C interface serial clock.
PGND
SW
PVIN
B2
N/A
SYNC
B3
C1
C2
C3
D1
D2
D3
2
8, PAD
7
3
6
5
4
AVIN
AGND
EN
SDA
VOUT
VSEL
SCL
Note:
5. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
2
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I C control is unused, tie SDA and SCL to AVIN.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.6
3
www.fairchildsemi.com
FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol
V
CC
ESD
T
J
T
STG
T
L
Parameter
AVIN, SW, PVIN Pins
Other Pins
Electrostatic Discharge Protection Level
Junction Temperature
Storage Temperature
Lead Soldering Temperature, 10 Seconds
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
Min.
-0.3
-0.3
3.5
1.5
–40
–65
Max.
6.5
AVIN + 0.3
(6)
Units
V
V
KV
KV
+150
+150
+260
°C
°C
°C
Note:
6. Lesser of 6.5V or AVIN+0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to absolute maximum ratings.
Symbol
V
IN
f
V
CCIO
T
A
T
J
Parameter
Supply Voltage
Frequency Range
SDA and SCL Voltage Swing
Ambient Temperature
Junction Temperature
(7)
Min.
2.7
2.7
–40
–40
Max.
5.5
3.3
2.5
+85
+125
Units
V
MHz
V
°C
°C
Note:
2
7. The I C interface operates with t
HD;DAT
= 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage
2
swings greater than 2.5V are required (for example if the I C bus is pulled up to V
IN
), the minimum t
HD;DAT
must be
2
increased to 80ns. Most I C masters change SDA near the midpoint between the falling and rising edges of SCL, which
provides ample t
HD;DAT
.
Dissipation Ratings
(8)
Package
Molded Leadless Package (MLP)
Wafer-Level Chip-Scale Package (WLCSP)
Rθ
JA
(9)
Power Rating at T
A
≤
25°C
2050mW
900mW
Derating Factor > T
A
= 25ºC
21mW/ºC
9mW/ºC
49ºC/W
110ºC/W
Notes:
8.
9.
Maximum power dissipation is a function of T
J(max)
,
θ
JA
, and T
A
. The maximum allowable power dissipation at any
allowable ambient temperature is P
D
= [T
J(max)
- T
A
] /
θ
JA
.
This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard).
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.6
4
www.fairchildsemi.com
FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator
Electrical Specifications
V
IN
= 3.6V, EN = V
IN
, VSEL = V
IN
, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. T
A
= -40°C to +85°C, unless otherwise
noted. Typical values are at T
A
= 25°C. Circuit and components according to Figure 1.
Symbol
V
IN
I
Q
Parameter
Input Voltage Range
Quiescent Current
Conditions
Min.
2.7
Typ.
Max.
5.5
Units
V
μA
mA
Power Supplies
I
O
= 0mA, PFM Mode
I
O
= 0mA, 3MHz PWM Mode
EN = GND
I
SD
Shutdown Supply Current
EN = V
IN
, EN_DCDC bit = 0,
SDA = SCL = V
IN
V
IN
Rising
V
IN
Falling
2.00
200
1.2
0.4
Input tied to GND or V
IN
V
IN
= 3.6V, CSP Package
R
DS(ON)P
I
LKGP
R
DS(ON)N
I
LKGN
R
DIS
P-Channel MOSFET On Resistance
P-Channel Leakage Current
N-Channel MOSFET On Resistance
N-Channel Leakage Current
Discharge Resistor for Power-Down
Sequence
V
IN
= 3.6V, MLP Package
V
IN
= 2.7V, MLP Package
V
DS
= 6V
V
IN
= 3.6V, CSP Package
V
IN
= 3.6V, MLP Package
V
IN
= 2.7V, MLP Package
V
DS
= 6V
Options 03 and 06
2.7V
≤
V
IN
≤
4.2V, Options 00 and 02
I
LIMPK
P-MOS Current Limit
2.7V
≤
V
IN
≤
5.5V, Options 00 and 02
2.7V
≤
V
IN
≤
4.2V, Options 03 and 06
2.7V
≤
V
IN
≤
5.5V, Options 03 and 06
T
LIMIT
T
HYST
f
SW
f
SYNC
D
SYNC
Thermal Shutdown
Thermal Shutdown Hysteresis
Oscillator Frequency
Synchronization Range
Synchronization Duty Cycle
2.65
2.7
20
1150
1050
1350
1250
60
1350
1350
1550
1550
150
20
3.00
3.0
3.35
3.3
80
75
95
101
1
120
1600
1600
1800
1800
°C
°C
MHz
MHz
%
mA
μA
Ω
mΩ
0.01
145
165
200
1
μA
mΩ
1.00
37
4.8
0.1
0.1
2.40
2.15
250
2.0
2.0
2.60
2.30
300
μA
V
V
mV
V
V
μA
50
V
UVLO
V
UVHYST
V
IH
V
IL
I
IN
Under-Voltage Lockout Threshold
Under-Voltage Lockout Hysteresis
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input Bias Current
ENABLE, VSEL, SDA, SCL, SYNC
Power Switch and Protection
Frequency Control
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.6
5
www.fairchildsemi.com
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