FAN6206 —Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
April 2010
FAN6206
Highly Integrated Dual-Channel Synchronous
Rectification Controller for Dual-Forward Converter
Features
Highly Integrated Dual-Channel SR Controller
Receives Synchronized Driving Signal from the
Primary Side
Internal Linear-Predict Timing Control for DCM
Operation
Ultra-Low V
DD
Operating Voltage for Different
Output Voltage of PC Power
V
DD
Over-Voltage Protection
14V Gate Driver Clamp
Description
The highly integrated FAN6206 is a dual-channel
synchronous rectification (SR) controller. FAN6206
allows design of a cost-effective power supply with
fewer external components, especially suited for dual-
forward topology used to obtain higher efficiency for
ATX power supplies.
The primary-side control method provides synchronous
rectification control for dual-forward converters that
operate in continuous conduction mode (CCM).
FAN6206 includes a proprietary linear-predict timing
control mechanism for dual-forward converters that
operate in discontinuous conduction mode (DCM) at
fixed or variable frequency. PWM frequency tracking
with secondary-side winding detection is provided by
adding dividing resistors. The primary-side signals are
generated from Fairchild’s FAN6210 (Primary-Side
Synchronous Rectifier Signal Trigger for Dual-Forward
Converter). The primary-side signals are transferred
through a pulse transformer to the secondary-side. The
benefits of this technique include simple control method
and improved power system reliability.
FAN6206 is available in 8-pin SOP package.
Applications
PC Power
Server Power
Open-Frame SMPS
Ordering Information
Part Number
FAN6206MY
Operating
Temperature Range
-40°C to +105°C
Package
8-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Marking Information
F:
Fairchild Logo
Z:
Plant Code
X:
Year Code
Y:
Week Code
TT:
Package Type
T:
M=SOP
P:
Y: Green Package
M:
Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1,2
3
4
5
6
7
8
Name
LPC1,
LPC2
SN
SP
VDD
GATE2
GND
GATE1
Description
Winding detection. This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE. An internal current source, I
CHG
, is determined according to the
voltage on the DET pin.
Synchronized signal to turn on SR. This pin is used to receive the “XN” signal from the primary
side to turn off the SR gate.
Synchronized signal to turn on SR. This pin is used to receive the “XP” signal from the primary-
side to turn-on the SR gate.
Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V,
respectively.
Driver output for freewheeling synchronous rectifier MOSFET.
Ground
Driver output for rectifying synchronous rectifier MOSFET.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
3
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
HV
V
L
P
D
Θ
JA
Ψ
jt
T
J
T
STG
T
L
ESD
DC Supply Voltage
SP, SN
LPC
Parameter
Min.
Max.
30
30
Unit
V
V
V
mW
°C/W
°C/W
°C
°C
°C
kV
-0.3
7.0
400
130
46
Power Dissipation at T
A
< 50°C
Junction to Ambient Thermal Resistance
Junction to Top Thermal Characteristics
Operating Junction Temperature
Storage Temperature Range
Lead Temperature, (Soldering 10 Seconds)
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
-40
-55
+125
+150
+260
4.00
1.25
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
T
A
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
°C
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
4
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Electrical Characteristics
V
DD
=20V, T
A
=25 , unless otherwise specified.
Symbol
V
DD
Section
V
OP
V
TH-ON1
V
TH-ON2
V
TH-OFF1
V
TH-OFF2
I
DD-OP
I
DD-ST
V
DD-OVP1
V
DD-OVP2
V
DD-OVP-HYS1
V
DD-OVP-HYS2
t
OVP1
t
OVP2
V
Z1
V
Z2
V
OL1
V
OL2
V
OH1
V
OH2
t
R1
t
R2
t
F1
t
F2
V
Z1
t
PD-HIGH-SP1
t
PD-HIGH-SP2
t
PD-LOW-SN1
t
PD-LOW-SN2
t
PD-LOW-LPC1
t
PD-LOW-LPC2
t
ON-MAX1
t
ON-MAX2
Parameter
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
Startup Current
V
DD
Over-Voltage Protection 1
V
DD
Over-Voltage Protection 2
Hysteresis Voltage for V
DD
OVP 1
Hysteresis Voltage for V
DD
OVP 2
V
DD
OVP Debounce Time 1
V
DD
OVP Debounce Time 2
Output Voltage Maximum (Clamp) 1
Output Voltage Maximum (Clamp) 2
Output Voltage LOW 1
Output Voltage LOW 2
Output Voltage HIGH 1
Output Voltage HIGH 2
Rising Time 1
Rising Time 2
Falling Time1
Falling Time 2
Output Voltage Maximum (Clamp)
Propagation Delay to OUT HIGH
Conditions
Min.
Typ.
Max.
25
Units
V
V
V
V
V
mA
μA
V
V
V
V
μs
μs
V
V
V
V
V
V
8.0
8.0
7.0
7.0
V
DD
=15V, DET=50KHz
V
DD
= 7.5V
20
20
1.2
1.2
40
40
V
DD
= 20V
V
DD
= 20V
V
DD
=12V, I
O
=50mA
V
DD
=12V, I
O
=50mA
V
DD
=12V, I
O
=50mA
V
DD
=12V, I
O
=50mA
V
DD
=12V, C
L
=7nF,
OUT=2V~9V
V
DD
=12V, C
L
=7nF,
OUT=2V~9V
V
DD
=12V, C
L
=7nF,
OUT=9V~2V
V
DD
=12V, C
L
=7nF,
OUT=9V~2V
V
DD
= 20V
t
R
+t
PD
,
(Trigger by SP),
|SP-SN|=5V
t
R
+t
PD
,
(Trigger by SN),
|SP-SN|=5V
t
R
+t
PD
,
(Trigger by LPC)
280
280
180
180
100
100
12
12
9
9
30
30
20
20
8.5
8.5
7.5
7.5
3
340
21
21
1.7
1.7
60
60
12
12
9.0
9.0
8.0
8.0
5
500
22
22
2.2
2.2
100
100
14
14
0.5
0.5
Output Drive for SR MOSFET Section
70
70
50
50
12
350
350
250
250
150
150
13
13
120
120
100
100
14
450
450
350
350
200
200
14
14
ns
ns
ns
ns
V
ns
Propagation Delay to OUT LOW
ns
Propagation Delay to OUT LOW
Maximum On Time
ns
μs
μs
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
5
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