FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
November 2010
FAN6204
Synchronous Rectification Controller for Flyback
and Forward Freewheeling Rectification
Features
SR Controller
Suited for Flyback Converter in QR, DCM, and
CCM Operation
Suited for Forward Freewheeling Rectification
Internal Green Mode for Lower No-Load Power
Consumption and Higher Light-Load Efficiency
PWM Frequency Tracking with Secondary-Side
Winding Voltage Detection
Ultra-Low V
DD
Operating Voltage for Various Output
Voltage Applications (5V~24V)
Ultra-Low Green Mode Operating Current:
1.1mA Typical
V
DD
Pin Over-Voltage Protection (OVP)
12V (Typical) Gate Driver Clamp
8-Pin SOP Package
Description
FAN6204 is a secondary-side synchronous rectification
(SR) controller to drive SR MOSFET for improving
efficiency. The IC is suitable for flyback converters and
forward free-wheeling rectification.
FAN6204 can be applied in continuous or discontinuous
conduction mode (CCM and DCM) and quasi-resonant
(QR) flyback converters based on the proprietary
innovative linear-predict timing-control technique. The
benefits of this technique include a simple control
method without current-sense circuitry to accomplish
noise immunity.
With PWM frequency tracking and secondary-side
winding voltage detection, FAN6204 can operate in both
fixed- and variable-frequency systems.
In Green Mode, the SR controller stops all SR switching
operation to reduce the operating current. Power
consumption is maintained at minimum level in light-
load condition.
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
FAN6204MY
Operating
Temperature Range
-40°C to +105°C
Package
8-Pin, Small Outline Package (SOP)
Packing Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Application Diagrams
Figure 1. Typical Application Circuit for
Flyback Converter
Figure 2. Typical Application Circuit for
Forward Freewheeling Rectification
Internal Block Diagram
GATE
3
VDD
5
950K
0.05V
DD
50K
4.8V/4.5V
Internal
Bias
+
-
+
OVP
Green
Mode
t
DIS
Q
PWM Block
Drive
Calculate
V
LPC-EN
V
LPC-EN
2V
27.5V/25.4V
1
AGND
2
AGND
6
AGND
-
S
-
LPC
8
Rising
Edge
Frequency
Tracking
Detector
t
SR-MAX
Causal
Function
RESET
+
0.05V
DD
1µs
Blanking
+
R Q
Enable
-
V
CT
i
CHR
i
DISCHR
C
T
RESET
1µA/V
5µA/V
7
RES
4
GND
Figure 3. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
2
FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Marking Information
: Fairchild Logo
Z:
Plant Code
X:
Year Code
Y:
Week Code
TT:
Die Run Code
T:
Package Type (N = DIP, M = SOP)
P:
Y = Green Package
M:
Manufacturing Flow Code
ZXYTT
6204
TPM
Figure 4. Marking Diagram
Pin Configuration
LPC
RES
AGND
VDD
8
7
6
5
1
2
3
GATE
4
GND
AGND AGND
Figure 5. Pin Assignments
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
AGND
AGND
GATE
GND
VDD
AGND
RES
LPC
Signal Ground
Signal Ground
Description
Driver Output.
The totem-pole output driver for driving the power MOSFET.
Ground.
MOSFET source connection.
Power Supply.
The threshold voltages for startup and turn-off are 4.8V and 4.5V, respectively.
Signal Ground
Reset Control
of linear predict. The RES pin is used to detect the output voltage level through
a voltage divider. An internal current source, I
DISCHR
, is modulated by the voltage level on the
RES pin.
Winding Detection.
This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE.
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
3
FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
L
P
D
Θ
JA
Θ
JC
T
STG
T
L
ESD
DC Supply Voltage
LPC, RES
Parameter
Min.
-0.3
Max.
30
7
45
151
58
Unit
V
V
W
°C/W
°C/W
°C
°C
KV
Power Dissipation(T
A
=25°C)
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
Storage Temperature Range
Lead Temperature (Soldering 10 Seconds)
Human Body Model
Charged Device Model
-55
+150
+260
5
2
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
T
A
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
°C
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
4
FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Electrical Characteristics
Unless otherwise specified, V
DD
=4.5V~25V and T
A
=-40°C ~ 105°C.
Symbol
V
OP
V
DD-ON
V
DD-OFF
I
DD-OP
I
DD-GREEN
I
DD-ST
V
DD-OVP
t
VDD-OVP
V
Z
V
OL
V
OH
t
R
t
F
t
PD_HIGH_LPC
t
PD_LOW_LPC
t
MAX-PERIOD
V
PMOS-ON
V
PMOS-ON-
HYS
Parameter
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
Operating Current in Green Mode
Startup Current
V
DD
Over-Voltage Protection
V
DD
OVP Debounce Time
Gate Output Clamp Voltage
Output Voltage Low
Output Voltage High
Rising Time
Falling Time
Propagation Delay to OUT HIGH
(LPC Trigger)
Propagation Delay to OUT LOW
(3)
(LPC Trigger)
Conditions
Min.
V
DD-
OFF
Typ.
Max.
28.5
Unit
V
V
V
mA
mA
μA
V
V
μs
V
V
V
ns
ns
ns
ns
ns
ns
4.3
4.0
V
DD
=15V, LPC=50KHz, MOSFET
C
ISS
=6000pF
V
DD
=15V
V
DD
< V
DD-ON
26
1.8
40
10
V
DD
=6V, I
O
=50mA
V
DD
=6V, I
O
=50mA
V
DD
=12V, CL=6nF, OUT=2V~9V
V
DD
=6V, CL=6nF, OUT=0.4V~4V
V
DD
=12V, CL=6nF, OUT=9V~2V
V
DD
=6V, CL=6nF, OUT=4V~0.4V
t
R
: 0V~2V, V
DD
= 12V
t
F
: 100%~90%, V
DD
= 12V
22.5
4
30
70
20
20
4.8
4.5
7
1.1
150
27.5
2.1
70
12
5.3
5.0
8
1.3
200
28.5
2.4
100
14
0.5
V
DD-OVP-HYST
Hysteresis Voltage for V
DD
OVP
Output Driver Section
70
120
50
90
250
180
25.0
8.3
0.9
120
170
100
130
Limitation between LPC Rising Edge to Gate Falling Edge
Internal PMOS Turn-On to Pull-HIGH Gate
Hysteresis Voltage On
Gate Inhibit Time
Gate Pull-HIGH Voltage
(3)
(3)
28.0
μs
V
V
t
INHIBIT
V
GATE-PULL-
HIGH
M2 Option (Enable)
V
DD
= 5V
1.6
4.5
2.2
2.8
μs
V
LPC Section
t
BNK
Blanking Time for Charging CT
(3)
400
Source I
LPC
=5µA
V
LPC
=0V
V
LPC-EN
= V
LPC-HIGH
x 0.83 at V
LPC-
HIGH
x 0.83< 2V, V
O
=15V, V
O
=V
DD
,
V
LPC-HIGH
= 1.2V
V
LPC-EN
=2V at V
LPC-HIGH
x 0.83 >
2V
0.05Vo+0.05, V
O
=15V, V
O
=V
DD
Prevent LPC Spike to Turn-Off
Gate
5
500
1
0.2
80
1.00
2
600
0.3
120
1.15
ns
μs
V
μA
V
V
t
DELAY-COMP
Sampling Continuous Time for t
BNK
Compensation
V
LPC-SOURCE
LPC Lower Clamp Voltage
I
LPC-SOURCE
LPC Source Current
V
LPC-EN
V
EN-CLAMP
V
LPC-TH-HIGH
t
BNK-DIS
SR Enabled Threshold Voltage
SR Enable Threshold Clamp
Voltage
Threshold Voltage on LPC Rising
Edge
Blanking Time LPC is HIGH
During SR Gate Turn-On Period
0.1
40
0.85
0.7
0.8
350
0.9
V
ns
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
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