Integrated
Circuit
Systems, Inc.
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Fully integrated PLL
•
Differential 3.3V LVPECL output
•
200MHz output frequency
•
48% to 52% duty cycle
•
Crystal oscillator interface
•
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI. Typical10dB EMI
reduction can be achieved with spread spectrum modulation
•
LVTTL / LVCMOS control inputs
•
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
•
28 lead SOIC
•
RMS cycle-to-cycle jitter of 2ps
•
Typical cycle-to-cycle jitter of 18ps
•
0° to 85°C ambiant operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8431-01 is a general purpose clock
frequency synthesizer for IA64/32 application and
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M is configured to
produce a fixed output frequency of 200MHz.
,&6
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
B
LOCK
D
IAGRAM
XTAL1
OSC
XTAL2
÷
16
P
IN
A
SSIGNMENT
nc
nc
nc
nc
nc
nc
nc
nc
nc
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
RESERVED
nc
VDDO
FOUT
nFOUT
VEE
PLL
PHASE
DETECTOR
VCO
÷
M
÷
2
FOUT
nFOUT
TEST_I/O
SSC_CTL0
SSC_CTL1
SSC
Control
Logic
ICS8431-01
28-Lead SOIC
M Package
Top View
ICS8431CM-01
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 5, 2001
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Unused
Input
Power
Input /
Output
Power
Power
Output
Power
Reserve
Power
Power
Input
Power
Pullup
Description
Unused pins.
SSC control pins. LVTTL/LVCMOS interface levels.
Ground pin for core and test output.
Programmed as defined in Table 3 Function Table..
Power supply pin for core and test output.
Ground pin for output.
These differential outputs are main output drivers for the synthesizer.
They are compatible with terminated positive referenced LVPECL
logic.
Power supply pin for output.
Reserve pin.
Ground pin.
PLL power supply pin.
Crystal oscillator input.
Input and core power supply pin. Connect to 3.3V.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1-9, 19,
23, 24, 28
10, 11
12
13
14, 27
15
16, 17
18
20
21
22
25, 26
27
Name
nc
SSC_CTL0,
SSC_CTL1
GND
TEST_ I/O
VDD
GND
nFOUT, FOUT
VDDO
RESERVED
VEE
VDDA
XTAL1, XTAL2
VDDI
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Pin Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
T
ABLE
3. SSC C
ONTROL
I
NPUTS
F
UNCTION
T
ABLE
Inputs
SSC_CTL1 SSC_CTL0
0
0
1
1
0
1
0
1
TEST_I/O
Source
Internal
PLL
External
PLL
SSC
Disabled
Enabled
Disabled
Disabled
Outputs
FOUT,
TEST_I/O
nFOUT
fXTAL
÷
16
fXTAL
÷
32
÷
M
200MHz
Hi-Z
Test Clk
200MHz
Input
Hi-Z
Operational Modes
PLL bypass; Oscillator, oscillator, M and N
dividers test mode. NOTE 1
Default SSC; Modulation Factor = ½ Percent
Diagnostic Mode; NOTE 1
(1MHz
≤
Test Clk
≤
200MHz)
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 5, 2001
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 85°C
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
VDD
VDDO
VDDA
VDDI
IEE
Parameter
Power Supply Voltage
Output Power Supply Voltage
Analog Power Supply Voltage
Input Power Supply Voltage
Test Conditions
Minimum
3.135
3.135
3.135
3.135
Typical
3.3
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
3.465
140
Units
V
V
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
VIH
Parameter
Input High Voltage
SSC_CTL0,
SSC_CTL1,
TEST_I/O
SSC_CTL0,
SSC_CTL1,
TEST_I/O
SSC_CTL0,
SSC_CTL1,
TEST_IO
SSC_CTL0,
SSC_CTL1,
TEST_IO
Test Conditions
3.135V
≤
VDD
≤
3.465V
3.135V
≤
VDD
≤
3.465V
Minimum
2
Typical
Maximum
VDD + 0.3
Units
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
5
µA
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-150
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
VOH
VOL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
Minimum
VDDO - 1.28
VDDO - 2.0
600
700
Typical
Maximum
VDDO - 0.980
VDDO - 1.7
850
Units
V
V
mV
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Output terminated with 50
Ω
to VDDO - 2V.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 5, 2001
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
Typical
16.666
-50
-100
+50
+100
100
50
3
10
3
0
Per year @25°C
-5
18
7
32
7
70
+5
Maximum
Units
MHz
ppm
ppm
µW
Ω
pF
pF
nH
°C
ppm
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Frequency Tolerance
Frequency Stability
Drive Level
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Load Capacitiance
Series Pin Inductance
Operating Temperature Range
Aging
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V±5%, T
A
= 0°C
TO
85°C, 16.666MH
Z
C
RYSTAL
Symbol
tPERIOD
Parameter
Average Output Period; NOTE 2
Cycle-to-Cycle Jitter ; NOTE 2
Output Duty Cycle; NOTE 2
Output Rise Time; NOTE 1, 2
Output Fall Time; NOTE 1, 2
Cr ystal Input Range
SSC Modulation Frequency;
NOTE 1, 2
SSC Modulation Factor ;
NOTE 1, 2
Spectral Reduction; NOTE 1, 2
Test Conditions
FOUT = 200 MHz
FOUT = 200 MHz
FOUT = 200 MHz
20% to 80%
20% to 80%
48
300
300
14
30
0.4
7
10
10
450
450
16.666
Minimum
4995
18
Typical
Maximum
5005
30
52
600
600
18
33.33
0.6
Units
ps
ps
%
ps
ps
MHz
KHz
%
dB
ms
t
j it(cc)
odc
tR
tF
Fxtal
Fm
Fmf
SSCred
tSTABLE
Power-up to Stable Clock Output
NOTE 1: Spread Spectrum clocking enabled.
NOTE 2: Outputs terminated with 50
Ω
to VDDO - 2V.
t
jit(cc), tR, tF, odc conform to JEDEC JESD65 definitions.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 5, 2001
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
80%
80%
Vswing
20%
Clock Inputs
and Outputs
➤
➤
20%
t
rise
AND
t
fall
➤
F
IGURE
1 — I
NPUT
X_CLK, 1X_FOUT
O
UTPUT
S
LEW
R
ATES
nX_CLK, n1X_FOUT
t
cycle
n
➤
t
cycle
n+1
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
F
IGURE
2 — C
YCLE
-
TO
-C
YCLE
J
ITTER
nX_CLK, n1X_FOUT
X_CLK, 1X_FOUT
Pulse Width (
t
pw)
➤
t
PERIOD
➤
odc =
t
pw
t
PERIOD
F
IGURE
3 — odc &
t
PERIOD
ICS8431CM-01
www.icst.com/products/hiperclocks.html
5
➤
➤
➤
➤
➤
➤
➤
REV. A JUNE 5, 2001
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