FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers
April 2011
FAN9611 / FAN9612
Interleaved Dual BCM PFC Controllers
Features
Sync-Lock™ Interleaving Technology for 180°
Out-of-Phase Synchronization Under All Conditions
Automatic Phase Disable at Light Load
Dead-Phase Detect Protection
2.0A Sink, 1.0A Source, High-Current Gate Drivers
High Power Factor, Low Total Harmonic Distortion
Voltage-Mode Control with (V
IN
)
2
Feedforward
Closed-Loop Soft-Start with User-Programmable
Soft-Start Time for Reduced Overshoot
Minimum Restart Frequency to Avoid Audible Noise
Maximum Switching Frequency Clamp
Brownout Protection with Soft Recovery
Non-Latching OVP on FB Pin and Latching Second-
Level Protection on OVP Pin
Open-Feedback Protection
Power-Limit and Current Protection for Each Phase
Low Startup Current of 80µA Typical
Works with DC and 50Hz to 400Hz AC Inputs
Description
The FAN9611/12 family of interleaved dual Boundary-
Conduction-Mode (BCM) Power-Factor-Correction (PFC)
controllers operate two parallel-connected boost power
trains 180° out of phase. Interleaving extends the
maximum practical power level of the control technique
from about 300W to greater than 800W. Unlike the
continuous conduction mode (CCM) technique often
used at higher power levels, BCM offers inherent zero-
current switching of the boost diodes, which permits the
use of less expensive diodes without sacrificing
efficiency. Furthermore, the input and output filters can
be smaller due to ripple current cancellation and effective
doubling of the switching frequency.
The converters operate with variable frequency, which is
a function of the load and the instantaneous input /
output voltages. The switching frequency is limited
between 16.5kHz and 525kHz. The Pulse Width
Modulators (PWM) implement voltage-mode control with
input voltage feedforward. When configured for PFC
applications, the slow voltage regulation loop results in
constant on-time operation within a line cycle. This PWM
method, combined with the BCM operation of the boost
converters, provides automatic power factor correction.
The controllers offers bias UVLO (10V / 7.5V for
FAN9611 and 12.5V / 7.5V for FAN9612), input
brownout, over-current, open-feedback, output over-
voltage, and redundant latching over-voltage protections.
Furthermore, the converters’ output power is limited
independently of the input RMS voltage. Synchronization
between the power stages is maintained under all
operating conditions.
Applications
100-1000W AC-DC Power Supplies
Large Screen LCD-TV, PDP-TV, RP-TV Power
High-Efficiency Desktop and Server Power Supplies
Networking and Telecom Power Supplies
Solar Micro Inverters
Figure 1. Simplified Application Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.3
www.fairchildsemi.com
FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers
Ordering Information
Part Number
FAN9611MX
FAN9612MX
Package
16-Lead, Small Outline Integrated Circuit (SOIC)
16-Lead, Small Outline Integrated Circuit (SOIC)
Packing Method
Tape and Reel
Tape and Reel
Packing
Quantity
2,500
2,500
This device passed wave soldering test by JESD22A-111.
Package Outlines
Figure 2. SOIC-16 (Top View)
Thermal Resistance Table
Thermal Resistance
Package
16-Lead SOIC
Suffix
M
Θ
JL
(1)
35°C/W
Θ
JA
(2)
50 – 120°C/W
(3)
Notes:
1. Typical
Θ
JL
is specified from semiconductor junction to lead.
2. Typical
Θ
JA
is dependent on the PCB design and operating conditions, such as air flow. The range of values
covers a variety of operating conditions utilizing natural convection with no heatsink on the package.
3. This typical range is an estimate; actual values depend on the application.
© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.3
www.fairchildsemi.com
2
FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers
Typical Application Diagram
V
IN
L2a
D2
V
LINE
R
ZCD2
C
IN
R
IN1
R
ZCD1
L1b
AC IN
EMI Filter
R
IN2
C
5VB
1
2
3
4
R
INHYST
R
MOT
C
SS
R
COMP
7
C
COMP,LF
C
COMP,HF
8
FB
OVP 9
C
VDD1
C
INF
C
VDD2
COMP
VIN 10
R
CS1
R
CS2
R
OV2
5
6
AGND
SS
DRV2 12
PGND 11
ZCD1
ZCD2
5VB
MOT
CS1 16
CS2 15
VDD 14
DRV1 13
V
BIAS
Q1
R
FB2
R
FB1
L2b
L1a
D1
V
OUT
C
OUT
R
G1
R
G2
Q2
R
OV1
Figure 3. Typical Application Diagram
Block Diagram
Figure 4. Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.3
www.fairchildsemi.com
3
FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers
Pin Configuration
Figure 5. Pin Layout (Top-View)
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
ZCD1
ZCD2
5VB
MOT
AGND
SS
COMP
FB
OVP
VIN
PGND
DRV2
DRV1
VDD
CS2
CS1
Description
Zero Current Detector for Phase 1
of the interleaved boost power stage.
Zero Current Detector for Phase 2
of the interleaved boost power stage.
5V Bias.
Bypass pin for the internal supply, which powers all control circuitry on the IC.
Maximum On-Time
adjust for the individual power stages.
Analog Ground.
Reference potential for all setup signals.
Soft-Start Capacitor.
Connected to the non-inverting input of the error amplifier.
Compensation Network
connection to the output of the g
M
error amplifier
Feedback pin
to sense the converter’s output voltage; inverting input of the error amplifier.
Output Voltage
monitor for the independent, second-level, latched OVP protection.
Input Voltage
monitor for brownout protection and input-voltage feedforward.
Power Ground
connection.
Gate Drive Output for Phase 2
of the interleaved boost power stage.
Gate Drive Output for Phase 1
of the interleaved boost power stage.
External Bias Supply
for the IC.
Current Sense Input for Phase 2
of the interleaved boost power stage.
Current Sense Input for Phase 1
of the interleaved boost power stage.
© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.3
www.fairchildsemi.com
4
FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
BIAS
Parameter
Supply Voltage to AGND & PGND
5VB Voltage to AGND & PGND
Voltage On Input Pins to AGND (Except FB Pin)
Voltage On FB Pin (Current Limited)
Voltage On Output Pins to PGND (DRV1, DRV2)
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
Max.
20.0
5.5
V
BIAS
+ 0.3
V
DD
+ 0.8
V
DD
+ 0.3
2.5
0.05
+260
Unit
V
V
V
V
V
A
A
ºC
ºC
ºC
I
OH,
I
OL
Gate Drive Peak Output Current (Transient)
Gate Drive Output Current (DC)
T
L
T
J
T
STG
Lead Soldering Temperature (10 Seconds)
Junction Temperature
Storage Temperature
-40
-65
+150
+150
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
DD
V
INS
I
SNK
I
SRC
Supply Voltage Range
Signal Input Voltage
Parameter
Min.
9
0
1.5
0.8
Typ.
12
Max.
18
5
Unit
V
V
A
A
Output Current Sinking (DRV1, DRV2)
Output Current Sourcing (DRV1, DRV2)
2.0
1.0
±5%
±10%
+125
L
MISMATCH
Boost Inductor Mismatch
(4)
T
A
Operating Ambient Temperature
-40
ºC
Note:
4. While the recommended maximum inductor mismatch is ±10% for optimal current sharing and ripple-current
cancellation, there is no absolute maximum limit. If the mismatch is greater than ±10%, current sharing is
proportionately worse, requiring over-design of the power supply. However, the accurate 180° out-of-phase
synchronization is still maintained, providing current cancellation, although its effectiveness is reduced.
© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.3
www.fairchildsemi.com
5
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