FDMF6704
The Xtra Small, High Performance, High Frequency DrMOS Module
August 2009
FDMF6704 - XS
TM
DrMOS
Benefits
The Xtra Small, High Performance, High Frequency DrMOS Module
General Description
Ultra compact size - 6 mm x 6 mm MLP, 44 % space
saving compared to conventional MLP 8 mm x 8 mm
DrMOS packages.
Fully optimized system efficiency.
Clean voltage waveforms with reduced ringing.
High frequency operation.
Compatible with a wide variety of PWM controllers in the
market.
tm
Features
Ultra- compact thermally enhanced 6 mm x 6 mm MLP
package 84 % smaller than conventional discrete solutions.
Synchronous driver plus FET multichip module.
High current handling of 35 A.
Over 93 % peak efficiency.
Tri-State PWM input.
Fairchild's PowerTrench
®
5 technology MOSFETs for clean
voltage waveforms and reduced ringing.
Optimized for high switching frequencies of up to 1 MHz.
Skip mode SMOD [low side gate turn off] input.
Fairchild SyncFET
TM
[integrated Schottky diode] technology
in the low side MOSFET.
Integrated bootstrap Schottky diode.
Adaptive gate drive timing for shoot-through protection.
Driver output disable function [DISB# pin].
Undervoltage lockout (UVLO).
Fairchild Green Packaging and RoHS
compliant. Low profile SMD package.
The XS
TM
DrMOS family is Fairchild’s next-generation fully-
optimized, ultra-compact, integrated MOSFET plus driver power
stage solutions for high current, high frequency synchronous
buck DC-DC applications. The FDMF6704 XS
TM
DrMOS
integrates a driver IC, two power MOSFETs and a bootstrap
Schottky diode into a thermally enhanced, ultra compact 6 mm x
6 mm MLP package. With an integrated approach, the complete
switching power stage is optimized with regards to driver and
MOSFET dynamic performance, system inductance and
R
DS(ON)
. This greatly reduces the package parasitics and layout
challenges associated with conventional discrete solutions.
uses
Fairchild's
high
performance
XS
TM
DrMOS
PowerTrench
TM
5 MOSFET technology, which dramatically
reduces ringing in synchronous buck converter applications.
PowerTrench
TM
5 can eliminate the need for a snubber circuit in
buck converter applications. The driver IC incorporates
advanced features such as SMOD for improved light load
efficiency and a Tri-State PWM input for compatibility with a
wide range of PWM controllers. A 5 V gate drive and an
improved PCB interface optimized for a maximum low side FET
exposed pad area, ensure higher performance. This product is
compatible with the new Intel 6 mm x 6 mm DrMOS
specification.
Applications
Compact blade servers V-core, non V-core and VTT DC-DC
converters.
Desktop computers V-core, non V-core and VTT DC-DC
converters.
Workstations V-core, non V-core and VTT DC-DC
converters.
Gaming Motherboards V-core, non V-core and VTT DC-DC
converters.
Gaming consoles.
High-current DC-DC Point of Load (POL) converters.
Networking and telecom microprocessor voltage regulators.
Power Train Application Circuit
5V
C
VDRV
VDRV VCIN
DISB#
PWM Input
OFF
ON
DISB#
PWM
SMOD#
CGND
VIN
BOOT
PHASE
VSWH
PGND
R
BOOT
C
BOOT
L
OUT
C
OUT
OUTPUT
12 V
C
VIN
Ordering Information
Order Number
FDMF6704
Marking
FDMF6704_1
Figure 1. Power Train Application Circuit
Temperature Range
-55 °C to 150 °C
Device Package
40 Pin, 3 DAP, MLP 6x6 mm
1
Packing Method
Tape and Reel
Quantity
3000
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©2008 Fairchild Semiconductor Corporation
FDMF6704 Rev. G
FDMF6704
The Xtra Small, High Performance, High Frequency DrMOS Module
Functional Block Diagram
VCIN
VDRV
BOOT
GH
VIN
Q1
DISB#
PWM
Overlap
Control
VSWH
SMOD#
VDRV
Q2
CGND
GL
PGND
Figure 2. Functional Block Diagram
Pin Configuration
SMOD#
VCIN
VDRV
BOOT
CGND
GH
PHASE
NC
VIN
VIN
10
1
2
3
4
5
6
7
8
9
10
9
8
7
6
5
4
3
2
PWM
DISB#
NC
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
11
CGND
41
VIN
42
12
13
14
15
16
VSWH
43
17
18
19
20
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
1
VIN
VIN
NC
PHASE
GH
CGND
BOOT
VDRV
VCIN
SMOD#
11
12
13
14
15
16
17
18
19
20
21
22
VIN
42
CGND
41
40
39
38
37
36
35
34
33
32
31
VSWH
43
PWM
DISB#
NC
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
23
24
25
26
27
28
29
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Bottom View
Figure 3. 6mm x 6mm, 40L MLP
FDMF6704 Rev. G
2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
Top View
30
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FDMF6704
The Xtra Small, High Performance, High Frequency DrMOS Module
Pin Description
Pin
1
2
3
4
5, 37, 41
6
7
8, 38
9-14, 42
15, 29-35, 43
16-28
36
39
40
Name
SMOD#
VCIN
VDRV
BOOT
CGND
GH
PHASE
NC
VIN
VSWH
PGND
GL
DISB#
PWM
Function
When SMOD# = HI, low side driver is inverse of PWM input. When SMOD# = Low, low
side driver is disabled. This pin has no internal pullup or pulldown. It should not be left
floating. Do not add noise filter cap.
IC bias supply. Minimum 1 F ceramic capacitor is recommended from this pin to CGND.
Power for low side driver. Minimum 1 F ceramic capacitor is recommended to be
connected as close as possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor from this pin to PHASE.
IC ground. Ground return for driver IC.
For manufacturing test only. This pin must be floated. Must not be connected to any pin.
Switch node pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin.
No connect.
Power input. Output stage supply voltage.
Switch node input. Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
Power ground. Output stage ground. Source pin of low side MOSFET(s).
For manufacturing test only. This pin must be floated. Must not be connected to any pin.
Output disable. When low, this pin disable FET switching (GH and GL are held low). This
pin has no internal pullup or pulldown. It should not be left floating. Do not add noise filter
cap.
PWM Signal Input. This pin accepts a Tri-state logic-level PWM signal from the controller.
Do not add noise filter cap.
Absolute Maximum Rating
Parameter
VCIN, VDRV, DISB#, PWM, SMOD#, GL to CGND
VIN to PGND, CGND
BOOT, GH to VSWH, PHASE
BOOT, VSWH, PHASE, GH to GND
BOOT to VDRV
I
O(AV)
*
I
O(peak)
*
R
θJPCB
Junction to PCB Thermal Resistance
-55
Operating and Storage Junction Temperature Range
V
IN
= 12 V, V
O
= 1.3 V
f
SW
= 350 kHz
f
SW
= 1 MHz
Min
Max
6
27
6
27
22
35
32
80
3.75
150
Units
V
V
V
V
V
A
A
A
°C/W
°
C
* I
O(AV)
and I
O(peak)
are measured in FCS evaluation board. These ratings can be changed with different application setting.
Recommended Operating Range
Parameter
V
CIN
V
IN
Control Circuit Supply Voltage
Output Stage Supply Voltage
Min
4.5
3
*
Typ
5
12
Max
5.5
14
Units
V
V
* May be operated at lower input voltage. See figure 10.
FDMF6704 Rev. G
3
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FDMF6704
The Xtra Small, High Performance, High Frequency DrMOS Module
Electrical Characteristics
V
IN
= 12 V, T
A
= 25 °C unless otherwise noted.
Parameter
Operating Quiescent Current
VCIN UVLO
UVLO Threshold
UVLO COMP Hysteresis
PWM Input
Sink Impedance
Source Impedance
Tri-State Rising Threshold
Hysteresis
Tri-State Falling Threshold
Hysteresis
Tri-State Pin Open
Tri-State Shut Off Time
SMOD# and DISB# Input
High Level Input Voltage
Low Level Input Voltage
Input Bias Current
Propagation Delay Time
High Side Driver
Rise Time
Fall Time
Deadband Time
Propagation Delay
Low Side Driver
Rise Time
Fall Time
Deadband Time
Propagation Delay
250 ns Time Out Circuit
250 ns Time Delay
Symbol
IQ
Conditions
PWM = GND
PWM = V
CIN
Min
Typ
Max
2
2
Units
mA
3.0
3.2
0.2
10
10
3.4
V
V
k
k
V
CIN
= 5 V
V
CIN
= 5 V
3.2
1.2
3.4
100
1.4
100
2.5
100
3.6
1.6
V
mV
V
mV
V
ns
V
2
0.8
-2
PWM = GND, delay between SMOD#
or DISB# from HI to LO to GL from HI
to LO.
10 % to 90 %
90 % to 10 %
t
DTHH
t
PDHL
GL going LO to GH going HI, 10 % to
10 %
PMW going LO to GH going LO
10 % to 90 %
90 % to 10 %
t
DTLH
t
PDLL
VSWH going LO to GL going HI, 10
% to 10 %
PWM going HI to GL going LO
Delay between GH from HI to LO and
GL from LO to HI.
15
2
V
A
ns
25
20
25
10
25
20
20
10
ns
ns
ns
ns
ns
ns
ns
ns
250
ns
FDMF6704 Rev. G
4
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FDMF6704
The Xtra Small, High Performance, High Frequency DrMOS Module
Description of Operation
Circuit Description
The FDMF6704 is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 1 MHz.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 4 for the
relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the GL pin. When the PWM signal goes HIGH, Q2 will begin
to turn OFF after some propagation delay (t
PDLL
). Once the GL
pin is discharged below 1 V, Q1 begins to turn ON after adaptive
delay t
DTHH
.
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the
VSWH pin. When the PWM signal goes LOW, Q1 will begin to
turn OFF after some propagation delay (t
PDHL
). Once the
VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive
delay t
DTLH
.
Additionally, V
GS
of Q1 is monitored. When V
GS(Q1)
is
discharged low, a secondary adaptive delay is initiated, which
results in Q2 being driven ON after 250 ns
,
regardless of VSWH
state. This function is implemented to ensure C
BOOT
is
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and VSWH voltage does not
fall below the 1 V adaptive threshold. The 250 ns secondary
delay is longer than t
DTLH
.
PWM
When the PWM input goes high, the high side MOSFET turns
on. When it goes low, the low side MOSFET turns on. When it is
open, both the low side and high side MOFET will turn off.
The DISB# input is combined with the PWM signal to control the
driver output. In a typical multiphase design, DISB# will be a
shared signal used to turn on all phases. The individual PWM
signals from the controller will be used to dynamically enable or
disable individual phases.
Low-Side Driver
The low-side driver (GL) is designed to drive a ground
referenced low R
DS(ON)
N-channel MOSFET. The bias for GL is
internally connected between VDRV and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB# = 0 V), GL
is held low.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (C
BOOT
). During
start-up, VSWH is held at PGND, allowing C
BOOT
to charge to
V
DRV
through the internal diode. When the PWM input goes
high, GH will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C
BOOT
and
delivered to Q1's gate. As Q1 turns on, VSWH rises to V
IN
,
forcing the BOOT pin to V
IN
+V
C(BOOT)
, which provides
sufficient VGS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling GH to VSWH. C
BOOT
is then
recharged to VDRV when VSWH falls to PGND. GH output is in
phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
SMOD
The SMOD (Skip Mode) function allows for higher converter
efficiency under light load conditions. During SMOD, the LS
FET is disabled and it prevents discharging of output caps.
When the SMOD# pin is pulled high, the sync buck converter
will work in synchronous mode. When the SMOD# pin is pulled
low, the LS FET is turned off. The SMOD function does not have
internal current sensing. This SMOD# pin is connected to a
PWM controller which enables or disables the SMOD
automatically when the controller detects light load condition.
Normally this pin is Active Low.
FDMF6704 Rev. G
5
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