FSEZ1317A — Primary-Side-Regulation PWM with POWER MOSFET Integrated
January 2011
FSEZ1317A
Primary-Side-Regulation PWM with POWER MOSFET
Integrated
Features
Low Standby Power Under 30mW
High-Voltage Startup
Fewest External Component Counts
Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
Green-Mode: Linearly Decreasing PWM Frequency
Fixed PWM Frequency at 50kHz with Frequency
Hopping to Solve EMI Problem
Cable Compensation in CV Mode
Peak-Current-Mode Control in CV Mode
Cycle-by-Cycle Current Limiting
V
DD
Over-Voltage Protection with Auto Restart
V
DD
Under-Voltage Lockout (UVLO)
Gate Output Maximum Voltage Clamped at 15V
Fixed Over-Temperature Protection with
Auto Restart
Available in the 7-Lead SOP Package
Description
This third-generation Primary-Side-Regulation (PSR)
and highly integrated PWM controller provides several
features to enhance the performance of low-power
flyback
converters.
The
proprietary
topology,
®
TRUECURRENT , of FSEZ1317A enables precise CC
regulation and simplified circuit design for battery-
charger applications. A low-cost, smaller, and lighter
charger results, as compared to a conventional design
or a linear transformer.
To minimize standby power consumption, the
proprietary green mode provides off-time modulation to
linearly decrease PWM frequency under light-load
conditions. Green mode assists the power supply in
meeting power conservation requirements.
By using the FSEZ1317A, a charger can be
implemented with few external components and
minimized cost. A typical output CV/CC characteristic
envelope is shown in Figure 1.
Applications
Battery chargers for cellular phones, cordless
phones, PDA, digital cameras, power tools, etc.
Replaces linear transformers and RCC SMPS
Figure 1. Typical Output V-I Characteristic
Ordering Information
Part Number
FSEZ1317AMY_F116
Operating
Temperature Range
-40°C to +105°C
Package
7-Lead, Small Outline Package (SOP-7)
Packing
Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FSEZ1317A • Rev. 1.0.1
www.fairchildsemi.com
FSEZ1317A — Primary-Side-Regulation PWM with POWER MOSFET Integrated
Application Diagram
R
sn
L
1
R
sn2
D
1
R
F
AC
Input
D
2
D
3
R
sn1
C
1
C
2
C
VDD
D
Fa
C
VS
2 VDD
7 HV
VS 5
DRAIN
8
1
C
sn2
T
1
C
sn
D
F
C
O1
D
sn
C
O2
R
d
DC
Output
D
4
R
1
R
2
CS
3 GND
COMR 4
R
SENSE
C
CR
Figure 2. Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FSEZ1317A • Rev. 1.0.1
www.fairchildsemi.com
2
FSEZ1317A — Primary-Side-Regulation PWM with POWER MOSFET Integrated
Marking Information
F:
Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP)
P: Y=Green Package
M: Manufacture Flow Code
Figure 4. Top Mark
Pin Configuration
Figure 5. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
7
8
Name
CS
VDD
GND
COMR
VS
HV
DRAIN
Description
Current Sense.
This pin connects a current-sense resistor, to detect the MOSFET current for
peak-current-mode control in CV mode, and provides the output-current regulation in CC mode.
Power Supply.
IC operating current and MOSFET driving current are supplied using this pin.
This pin is connected to an external V
DD
capacitor of typically 10µF. The threshold voltages for
startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA.
Ground
Cable Compensation.
This pin connects a 1µF capacitor between the COMR and GND pins
for compensation voltage drop due to output cable loss in CV mode.
Voltage Sense.
This pin detects the output voltage information and discharge time based on
voltage of auxiliary winding.
High Voltage.
This pin connects to bulk capacitor for high-voltage startup.
Driver Output.
Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317A • Rev. 1.0.1
www.fairchildsemi.com
3
FSEZ1317A — Primary-Side-Regulation PWM with POWER MOSFET Integrated
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
HV
V
VDD
V
VS
V
CS
V
COMV
V
COMI
V
DS
I
D
I
DM
E
AS
I
AR
P
D
θ
JA
Ψ
JT
T
J
T
STG
T
L
ESD
HV Pin Input Voltage
DC Supply Voltage
(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
Parameter
Min.
Max.
500
30
Units
V
V
V
V
V
V
V
A
A
A
mJ
A
mW
°C/W
°C/W
°C
°C
°C
V
-0.3
-0.3
-0.3
-0.3
7.0
7.0
7.0
7.0
700
1
0.6
4
50
1
660
150
39
Voltage Error Amplifier Output Voltage
Current Error Amplifier Output Voltage
Drain-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
Power Dissipation (T
A
＜50°C)
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
Operating Junction Temperature
Storage Temperature Range
Lead Temperature (Wave soldering or IR, 10 seconds)
Electrostatic
Human Body Model, JEDEC-JESD22_A114
Discharge Capability
Charged Device Model, JEDEC-JESD22_C101
(Except HV Pin)
T
A
=25°C
T
A
=100°C
-40
-55
5000
2000
+150
+150
+260
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
3. ESD ratings including HV pin: HBM=500V, CDM=1250V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
T
A
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Units
°C
© 2010 Fairchild Semiconductor Corporation
FSEZ1317A • Rev. 1.0.1
www.fairchildsemi.com
4
FSEZ1317A — Primary-Side-Regulation PWM with POWER MOSFET Integrated
Electrical Characteristics
Unless otherwise specified, V
DD
=15V and T
A
=25℃.
Symbol
V
DD
Section
V
OP
V
DD-ON
V
DD-OFF
I
DD-OP
I
DD-GREEN
V
DD-OVP
V
DD-OVP-HYS
t
D-VDDOVP
V
HV-MIN
I
HV
I
HV-LC
Parameter
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
Green-Mode Operating Supply Current
V
DD
Over-Voltage-Protection Level (OVP)
Hysteresis Voltage for V
DD
OVP
V
DD
Over-Voltage-Protection Debounce Time
Minimum Startup Voltage on HV Pin
Supply Current Drawn from HV Pin
Leakage Current after Startup
Conditions
Min.
Typ.
Max. Units
23
V
V
V
mA
mA
V
2.5
300
50
V
µs
V
mA
µA
15
4.5
16
5.0
2.5
0.95
24
17
5.5
5.0
1.45
1.5
50
2.0
200
HV Startup Current Source Section
V
DC
=100V
HV=500V,
V
DD
= V
DD-
OFF
+1V
47
1.5
0.96
3.0
3.00
Oscillator Section
f
OSC
f
OSC-N-MIN
f
OSC-CM-MIN
f
DV
f
DT
Frequency
Center Frequency
Frequency Hopping Range
50
±3.5
370
13
V
DD
=10~25V,
T
A
=-40°C to
105°C
10
R
VS
=20kΩ
1.4
90
600
725
0.8
2.475
f
OSC
-5kHz
f
OSC
=1kHz
2.475
2.500
2.2
0.4
2.500
0.85
2.525
2.525
200
950
1
2
15
53
kHz
Hz
kHz
%
%
Minimum Frequency at No-Load
Minimum Frequency at CCM
Frequency Variation vs. V
DD
Deviation
Frequency Variation vs. Temperature Deviation
Voltage-Sense Section
I
tc
V
BIAS-COMV
t
PD
t
MIN-N
V
TH
V
VR
V
N
V
G
V
IR
V
COMR
IC Bias Current
Adaptive Bias Voltage Dominated by V
COMV
Propagation Delay to GATE Output
Minimum On Time at No-Load
Threshold Voltage for Current Limit
Reference Voltage
Green-Mode Starting Voltage on EA_V
Green-Mode Ending Voltage on EA_V
Reference Voltage
COMR Pin for Cable Compensation
µA
V
ns
ns
V
V
V
V
V
V
Current-Sense Section
Voltage-Error-Amplifier Section
Current-Error-Amplifier Section
Cable Compensation Section
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FSEZ1317A • Rev. 1.0.1
www.fairchildsemi.com
5
Microcontroller MCU
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