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SG5726445DHE6CH01

Description
DRAM
Categorystorage    storage   
File Size195KB,21 Pages
ManufacturerSMART Modular Technology Inc
Download Datasheet Parametric Compare View All

SG5726445DHE6CH01 Overview

DRAM

SG5726445DHE6CH01 Parametric

Parameter NameAttribute value
MakerSMART Modular Technology Inc
package instruction,
Reach Compliance Codeunknown

SG5726445DHE6CH01 Preview

SU5726445DHE6CU01
December 26, 2007
Ordering Information
Part Numbers
SG5726445DHE6CL01
Description
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx4 Based, DDR333B, 30.48mm, 22Ω DQ termination,
Low Power, Green Module (RoHS Compliant).
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx4 Based, DDR266A, 30.48mm, 22Ω DQ termination,
Low Power, Green Module (RoHS Compliant).
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx4 Based, DDR266B, 30.48mm, 22Ω DQ termination,
Low Power.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx4 Based, DDR266B, 30.48mm, 22Ω DQ termination,
Low Power, Green Module (RoHS Compliant).
Module Speed
PC2700 @ CL 2.5
SG5726445DHE6CG01
PC2100 @ CL 2.0, 2.5
SM5726445DHE6CH01
PC2100 @ CL 2.5
SG5726445DHE6CH01
PC2100 @ CL 2.5
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU5726445DHE6CU01
December 26, 2007
Revision History
• December 26, 2007
Added SG5726445DHE6CL01 to the datasheet to represent the new Module Speed.
Obsoleted SM5726445DHE6CG01, SB5726445DHE6CG01, SX5726445DHE6CG01, SB5726445DHE6CH01 &
SX5726445DHE6CH01 because the Module Process Technologies are no longer available.
• August 20, 2004
Changed the datasheet part number from SM5726445DHE6CU01 to SU5726445DHE6CU01 because of the
addition of new Module Process Technologies.
Added SB5726445DHE6CG01, SX5726445DHE6CG01, SG5726445DHE6CG01, SB5726445DHE6CH01,
SX5726445DHE6CH01 & SG5726445DHE6CH01 to the datasheet to represent the new Module Process Tech-
nologies.
• May 6, 2004
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU5726445DHE6CU01
December 26, 2007
512MByte (64Mx72) DDR SDRAM Module - 64Mx4 Based
184-pin DIMM, Registered, ECC
Features
• Standard
• Configuration
• Cycle Time
:
:
:
JEDEC
ECC
6.0ns (PC2700)
7.5ns (PC2100)
2.0, 2.5
2, 4, 8
Sequential/Interleave
4
Operating Voltage :
2.5V
Refresh
:
8K/64ms Low Power
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
133.35mm x 30.48mm
No. of sides
:
Single-sided
Mating Connector (Examples)
Vertical
:
AMP - 5390241-1
CAS# Latency
:
Burst Length
:
Burst Type
:
No. of Internal
Banks per SDRAM :
DDR 184-pin DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DDQ
NC
NC
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
Pin Pin
No. Name
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
Pin Pin
No. Name
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DDQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
Pin Pin
No. Name
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
NC
NC
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Pin
No.
93
94
95
96
97
98
99
Pin
Name
V
SS
DQ4
DQ5
V
DDQ
DM0
DQ6
DQ7
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
116 V
SS
117 DQ21
118 A11
119 DM2
120 V
DD
121 DQ22
122 A8
123 DQ23
124 V
SS
125 A6
126 DQ28
127 DQ29
128 V
DDQ
129 DM3
130 A3
131 DQ30
132 V
SS
133 DQ31
139 V
SS
140 DM8
141 A10
142 CB6
143 V
DDQ
144 CB7
145 V
SS
146 DQ36
147 DQ37
148 V
DD
149 DM4
150 DQ38
151 DQ39
152 V
SS
153 DQ44
154 RAS#
155 DQ45
156 V
DDQ
157 CS0#
162 DQ47
163 NC
164 V
DDQ
165 DQ52
166 DQ53
167 NC
168 V
DD
169 DM6
170 DQ54
171 DQ55
172 V
DDQ
173 NC
174 DQ60
175 DQ61
176 V
SS
177 DM7
178 DQ62
179 DQ63
180 V
DDQ
100 V
SS
101 NC
102 NC
103 NC
104 V
DDQ
105 DQ12
106 DQ13
107 DM1
108 V
DD
109 DQ14
110 DQ15
111
CKE1 (NC) 134 CB4
135 CB5
136 V
DDQ
137 CK0
138 CK0#
112 V
DDQ
113 NC
114 DQ20
115 A12
158 CS1# (NC) 181 SA0
159 DM5
160 V
SS
161 DQ46
182 SA1
183 SA2
184 V
DDSPD
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU5726445DHE6CU01
December 26, 2007
Pin Description Table
Symbol
CK0
CK0#
CKE0
CS0#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Polarity
Positive
Edge
Negative
Edge
Active High
Active Low
Active Low
-
-
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
(All DDR SDRAM addr/cntl inputs are sampled on the rising edge of their associated clocks.)
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM
PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the opera-
tions to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,
CA11) when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, auto-
precharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autopre-
charge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of
BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
Data strobe for input and output data.
DQ0~DQ63
CB0~CB7
DM0~ DM8
DQS0~DQS8
SSTL
SSTL
SSTL
-
Active High
Negative &
Positive
Edge
-
-
SA0~SA2
SDA
LVTTL
LVTTL
These signals are tied on the system to either V
SS
or V
DD
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected on the system board from the SDA bus line to V
DDSPD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
on the system board from the SCL bus line to V
DDSPD
to act as a pullup.
This signal is asynchronous and driven low to the register to guarantee that the register outputs
are low.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which sup-
ports both 2.3 Volt and 3.3 Volt operation).
No Connect.
SCL
LVTTL
-
RESET#
V
DD,
V
SS
V
REF
V
DDQ
V
DDSPD
NC
LV-
CMOS
Supply
Supply
Supply
Supply
-
Active Low
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU5726445DHE6CU01
December 26, 2007
Block Diagram
RCS0#
RCKE0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQ8
DQ9
DQ10
DQ11
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQ24
DQ25
DQ26
DQ27
DQS8
CB0
CB1
CB2
CB3
DQS4
DQ32
DQ33
DQ34
DQ35
DQS5
DQ40
DQ41
DQ42
DQ43
DQS6
DQ48
DQ49
DQ50
DQ51
DQS7
DQ56
DQ57
DQ58
DQ59
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
DQS9
DQ4
DQ5
DQ6
DQ7
DQS10
DQ12
DQ13
DQ14
DQ15
DQS11
DQ20
DQ21
DQ22
DQ23
DQS12
DQ28
DQ29
DQ30
DQ31
DQS17
CB4
CB5
CB6
CB7
DQS13
DQ36
DQ37
DQ38
DQ39
DQS14
DQ44
DQ45
DQ46
DQ47
DQS15
DQ52
DQ53
DQ54
DQ55
DQS16
DQ60
DQ61
DQ62
DQ63
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
22Ω
DQS S# CKE
22Ω
I/O 0
22Ω
I/O 1
22Ω
I/O 2
22Ω
I/O 3
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5

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