CY7C1445V33-250AC datasheet, PDF

Datasheet> All Categories > storage> storage> CY7C1445V33-250AC

CY7C1445V33-250AC: DescriptionCache SRAM, 2MX18, 2.7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100; Categorystorage storage; File Size507KB，28 Pages; ManufacturerCypress Semiconductor

Download Datasheet Parametric View All

CY7C1445V33-250AC Overview

Cache SRAM, 2MX18, 2.7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

CY7C1445V33-250AC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.7 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	37748736 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Minimum standby current	3.14 V
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD (800)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

Preview

Download Datasheet

View All

PRELIMINARY

CY7C1444V33

CY7C1445V33

1M x 36/2M x 18 Pipelined DCD SRAM

Features

•

Fast clock speed: 250, 200, and 167 MHz

Provide high-performance 3-1-1-1 access rate

Fast access time: 2.7, 3.0 and 3.5 ns

Optimal for depth expansion

Single 3.3V –5% and +5% power supply V

Separate V

DDQ

for 3.3V or 2.5V

Common data inputs and data outputs

Byte Write Enable and Global Write control

Chip enable for address pipeline

Address, data, and control registers

Internally self-timed Write Cycle

Burst control pins (interleaved or linear burst

sequence)

Automatic power-down for portable applications

High-density, high-speed packages

JTAG boundary scan for BGA packaging version

Available in 119-ball bump BGA,165-ball FBGA and

100-pin TQFP packages (CY7C1444V33 and

CY7C1445V33)

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,

BWc, BWd and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQ

a,b,c,d

) and the data

parity (DP

a,b,c,d

) outputs, enabled by OE, are also

asynchronous.

a,b,c,d

and DP

a,b,c,d

apply to CY7C1444V33, and DQ

a,b

and

a,b

apply to CY7C1445V33. a, b, c, d each are eight bits

wide in the case of DQ and 1 bit wide in the case of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa and DPa. BWb controls DQb and DPb. BWc

controls DQc and DPd. BWd controls DQ and DPd. BWa,

BWb, BWc, BWd can be active only with BWE being LOW. GW

being LOW causes all bytes to be written. WRITE

pass-through capability allows written data available at the

output for the immediately next READ cycle. This device also

incorporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

The CY7C1444V33/CY7C1445V33 are both double-cycle

deselect parts.All inputs and outputs of the CY7C1444V33,

CY7C1445V33 are JEDEC-standard JESD8-5-compatible.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1444V33 and CY7C1445V33 SRAMs integrate

1,048,576 x 36/2,097,152 x18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

Selection Guide

[1]

CY7C1444V33

CY7C1445V33

-300

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Note:

1. Shaded areas contain advance information.

CY7C1444V33

CY7C1445V33

-250

2.7

TBD

CY7C1444V33

CY7C1445V33

-200

3.0

TBD

CY7C1444V33

CY7C1445V33

-167

Unit

3.5

TBD

2.3

Com’l

TBD

Cypress Semiconductor Corporation

Document #: 38-05189 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 13, 2002

Recommended Resources

Charge-discharge IGBT turn-off snubber circuit

FKL-32 type thyristor automatic excitation device circuit a

Electronic bird circuit that does not cry at night

Slow logic pulse listener circuit diagram

555 fully automatic home appliance protector circuit

Bistable circuit without reverse bias

Intelligent temperature control fan based on 51 single chip microcomputer: Use DS18B20 to collect temperature and use DC motor as fan. Request a program with simulation...; jiangandlin 51mcu

IGBT dead zone definition: IGBT dead zone: ensures reliable opening and closing of IGBT. IGBT is a power semiconductor device, which is widely used in industrial fields such as variable frequency speed regulation and reactive p...; eeleader Industrial Control Electronics

Problems with creating applications with platform builder 5.0: I created a new project, compiled it, built a helloworld application, and wanted to change the icon. It turns out that I can add the icon, but I can't delete it. The delete key on the keyboard doesn't...; caobenda Embedded System

st7 timer usage: I am using the ST7FLITE05YOM6 chip, and there is a problem when using the LITE timer. The source code is as follows, and the main function is a one-second delay. I would like to ask why this source co...; pansq stm32/stm8

Motor drive: Does anyone have a DC brushed motor or DC brushless motor drive circuit diagram that uses all discrete components? Please share it with me. [b][color=#5E7384]This content was originally created by EEW...; Alpha_gao Motor Drive Control（Motor Control）

DSP281x read and write EEPROM 24C02 programming routine: The source program is as follows: /*******************************************************************/ /*Copyright (C), 2008-2009, LiTian Tech.Co.Ltd. */ /* Module Name : GPIO */ /* File Name : main....; Jacktang DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components