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Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> BUK107-50DLT/R
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BUK107-50DLT/R

Description
IC BUF OR INV BASED PRPHL DRVR, PLASTIC PACKAGE-4, Peripheral Driver
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size60KB，9 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric View All

BUK107-50DLT/R Overview

IC BUF OR INV BASED PRPHL DRVR, PLASTIC PACKAGE-4, Peripheral Driver

BUK107-50DLT/R Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNXP
package instructionPLASTIC PACKAGE-4
Contacts4
Reach Compliance Codeunknown
ECCN codeEAR99
Interface integrated circuit typeBUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-609 codee3
Output current flow directionSINK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Terminal surfaceMatte Tin (Sn)
Maximum time at peak reflow temperatureNOT SPECIFIED

BUK107-50DLT/R Preview

Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic overload protected logic
level power MOSFET in a surface
mount plastic envelope, intended as
a general purpose switch for
automotive systems and other
applications.
BUK107-50DL
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
D
T
j
R
DS(ON)
PARAMETER
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
MAX.
50
0.7
1.8
150
200
UNIT
V
A
W
˚C
mΩ
APPLICATIONS
General controller for driving
lamps
small motors
solenoids
FEATURES
Vertical power DMOS output
stage
Overload protected up to
85˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
INPUT
RIG
POWER
MOSFET
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN
1
2
3
4
input
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
D
TOPFET
I
P
1
2
3
S
March 1997
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
I
D
I
I
I
IRM
P
D
T
stg
T
j
PARAMETER
Continuous drain source voltage
1
Continuous drain current
2
Continuous input current
Non-repetitive peak input current
Total power dissipation
Storage temperature
Continuous junction temperature
CONDITIONS
-
-
clamping
t
p
≤
1 ms
T
amb
= 25 ˚C
-
normal operation
3
MIN.
-
-
-
-
-
-55
-
BUK107-50DL
MAX.
50
self limiting
3
10
1.8
150
150
UNIT
V
A
mA
mA
W
˚C
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model;
C = 250 pF; R = 1.5 kΩ
MIN.
-
MAX.
2
UNIT
kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
E
DSM
E
DRM
PARAMETER
Non-repetitive clamping energy
Repetitive clamping energy
CONDITIONS
T
b
≤
25 ˚C; I
DM
< I
D(lim)
;
inductive load
T
b
≤
75 ˚C; I
DM
= 50 mA;
f = 250 Hz
MIN.
-
-
MAX.
100
4
UNIT
mJ
mJ
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOL
V
DDP
PARAMETER
CONDITIONS
MIN.
-
-
MAX.
35
16
UNIT
V
V
Protected drain source supply voltage V
IS
= 5 V
V
IS
= 4 V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition.
It remains latched off until reset by the input.
SYMBOL
I
D(lim)
T
j(TO)
PARAMETER
Overload protection
Drain current limiting
V
IS
= 5 V
0.7
100
1.1
130
1.5
160
A
˚C
Overtemperature protection
only in drain current limiting
Threshold junction temperature V
IS
= 5 V
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1
Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2
Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not
in an overload condition with drain current limiting.
March 1997
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL
R
th j-sp
R
th j-b
R
th j-a
PARAMETER
Thermal resistance
Junction to solder point
Junction to board
1
Junction to ambient
CONDITIONS
MIN.
-
-
-
BUK107-50DL
TYP.
12
40
-
MAX.
18
-
70
UNIT
K/W
K/W
K/W
Mounted on any PCB
Mounted on PCB of fig. 19
STATIC CHARACTERISTICS
T
b
= 25 ˚C unless otherwise specified
SYMBOL
V
(CL)DSS
V
(CL)DSS
I
DSS
I
DSS
I
DSS
R
DS(ON)
PARAMETER
Drain-source clamping voltage
Drain-source clamping voltage
Off-state drain current
Off-state drain current
Off-state drain current
Drain-source on-state
resistance
2
CONDITIONS
V
IS
= 0 V; I
D
= 10 mA
V
IS
= 0 V; I
DM
= 200 mA;
t
p
≤
300
µs; δ ≤
0.01
V
DS
= 45 V; V
IS
= 0 V
V
DS
= 50 V; V
IS
= 0 V
V
DS
= 40 V; V
IS
= 0 V; T
j
= 100 ˚C
V
IS
= 5 V; I
DM
= 100 mA;
t
p
≤
300
µs; δ ≤
0.01
MIN.
50
-
-
-
-
-
TYP.
55
56
0.5
1
10
150
MAX.
-
70
2
20
100
200
UNIT
V
V
µA
µA
µA
mΩ
INPUT CHARACTERISTICS
T
b
= 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL
V
IS(TO)
I
IS
I
ISL
V
ISR
V
(CL)IS
R
IG
PARAMETER
Input threshold voltage
Input supply current
Input supply current
Protection latch reset voltage
3
Input clamping voltage
Input series resistance
CONDITIONS
V
DS
= 5 V; I
D
= 1 mA
normal operation;
protection latched;
V
IS
= 5 V
V
IS
= 4 V
V
IS
= 5 V
V
IS
= 3.5 V
MIN.
1.7
-
-
-
-
1
6
-
TYP.
2.2
330
170
500
250
2.2
7.5
33
MAX.
2.7
450
270
650
400
3.5
-
-
UNIT
V
µA
µA
µA
µA
V
V
kΩ
I
I
= 1.5 mA
to gate of power MOSFET
SWITCHING CHARACTERISTICS
T
amb
= 25 ˚C; resistive load R
L
= 50
Ω;
adjust V
DD
to obtain I
D
= 250 mA; refer to test circuit and waveforms
SYMBOL
t
d on
t
r
t
d off
t
f
PARAMETER
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
IS
= 5 V to V
IS
= 0 V
CONDITIONS
V
IS
= 0 V to V
IS
= 5 V
MIN.
-
-
-
-
TYP.
8
30
3
6
MAX.
-
-
-
-
UNIT
µs
µs
µs
µs
1
Temperature measured 1.3 mm from tab.
2
Continuous input voltage. The specified pulse width is for the drain current.
3
The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
a
Normalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
20
40
60
80
100
Tmb / C
120
140
0
-60 -40 -20
0
20
40 60
Tj / C
80
100 120 140
Fig.2. Normalised limiting power dissipation.
P
D
% = 100
⋅
P
D
/P
D
(25 ˚C) = f(T
mb
)
ID / A
BUK107-50DL
CURRENT LIMITING OCCURS
WITHIN THE SHADED REGION
Fig.5. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)
25 ˚C = f(T
j
); I
D
= 100 mA; V
IS
= 5 V
RDS(ON) / mOhm
240
200
160
MAX.
BUK107-50DL
2.0
1.5
TYP.
1.0
TYP.
120
80
0.5
40
0
0
20
40
60
80
Tamb / C
100
120
140
0
0
2
4
VIS / V
6
8
10
Fig.3. Continuous drain current.
I
D
= f(T
amb
); condition: V
IS
= 5 V
ID / A
VIS / V =
BUK107-50DL
7
6
1
5
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
IS
); conditions: I
D
= 100 mA, t
p
= 300
µ
s
ID / A
BUK107-50DL
1.5
1.5
1
4
0.5
0.5
0
0
4
8
12
16
VDS / V
20
24
28
32
0
0
2
4
VIS / V
6
8
10
Fig.4. Typical on-state characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
IS
; t
p
= 300
µ
s
Fig.7. Typical transfer characteristics, T
j
= 25 ˚C.
I
D
= f(V
IS
); conditions: V
DS
= 10 V, t
p
= 300
µ
s
March 1997
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
200
180
160
140
Tj(TO) / C
BUK107-50DL
VIS(TO) / V
BUK107-50DL
3
MAX.
TYP.
TYP.
2
MIN.
120
100
80
60
0
2
4
VIS / V
6
8
10
1
-50
0
50
Tj / C
100
150
Fig.8. Typical overtemperature protection threshold.
T
j(TO)
= f(V
IS
); condition: V
DS
= 10 V
IIS & IISL / mA
BUK107-50DL
Fig.11. Input threshold voltage.
V
IS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= 5 V
II / mA
BUK107-50DL
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
9
8
LATCHED
7
6
5
NORMAL
RESET
IISL
IIS
4
3
2
1
0
0
2
4
VIS / V
6
8
0
2
4
VIS / V
6
8
10
Fig.9. Typical DC input characteristics, T
j
= 25 ˚C.
I
IS
& I
ISL
= f(V
IS
); normal operation & protection latched
IIS / uA
VIS / V =
400
BUK107-50DL
Fig.12. Typical input clamping characteristic.
I
I
= f(V
IS
); normal operation, T
j
= 25 ˚C.
ID / mA
BUK107-50DL
500
200
150
5V
300
TYP.
100
200
4V
100
50
0
-50
0
50
Tj / C
100
150
0
50
52
54
VDS / V
56
58
60
Fig.10. Typical DC input current.
I
IS
= f(T
j
); parameter V
IS
; normal operation
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
I
D
= f(V
DS
); conditions: V
IS
= 0 V; t
p
≤
300
µ
s
March 1997
5
Rev 1.200
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