CD-700KACGEB-65.536 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> CD-700KACGEB-65.536

CD-700KACGEB-65.536: DescriptionPHASE LOCKED LOOP, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size147KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

CD-700KACGEB-65.536 Overview

PHASE LOCKED LOOP, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16

CD-700KACGEB-65.536 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
Parts packaging code	SOIC
package instruction	QCCN,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.13 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	GOLD OVER NICKEL
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	5.08 mm

Preview

Download Datasheet

View All

CD-700

Complete VCXO Based Phase Lock Loop

Features

•

5 x 7.5 x 2 mm, smallest VCXO PLL available

•

Output Frequencies to 65.536 MHz

•

5.0 or 3.3 Vdc operation

•

Tri-State Output

•

Loss of Signal Alarm

•

VCXO with CMOS outputs

•

0/70 or –40/85

°C

temperature range

•

Hermetically sealed ceramic SMD package

Applications

•

Frequency Translation

•

Clock Smoothing, Clock Switching

•

NRZ Clock recovery

LOS

(8)

PHO OPN

(3)

(2)

OPOUT

(1)

(16)

LOSIN

(4)

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low jitter PLL’s

DATAIN

(5)

CLKIN

(6)

VCXO

Phase

Detector

and LOS

OP-Amp

OUT1

(13)

Description

Optional

2 Divider

OUT2

(11)

RCLK RDATA

(9)

(10)

OPP

(15)

GND

(7)

VDD

(14)

HIZ

(12)

The VI CD-700 is a user-configurable crystal

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Figure 1. CD-700 Block Diagram

Vectron International 166 Glover Avenue, Norwalk CT 06856-5160

Tel:1-88-VECTRON-1

e-mail: vectron@vectron.com

CD-700, VCXO Based PLL

CD-700 Theory of Operation

Phase Detector

The phase detector has two buffered inputs (DATAIN and CLKIN) which are designed to switch at

1.4 volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which

have a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for

a block diagram and Figure 5 for an open loop transfer curve). This will simplify the PLL design as the

designer does not have to filter narrow pulse signals to a DC level. Under locked conditions the rising

edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).

The phase detector gain is 0.53V/rad x data density for 5volt operation and 0.35V/rad x data density for

3.3 volt operation. Data density is equal to 1.0 for clock signals and is system dependent on coding and

design for NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1 MHz but produces

significant ripple when inputs are less than 200 kHz. Additional filtering is required for lower input

frequencies applications such as 8kHz (see Figures 8 and 9 as examples).

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain,

so under normal locked conditions and input frequencies >1 MHz, PHO will be about V

/2 and will not

vary significantly with changes in input frequency (within lock range). The control voltage (pin 16) will vary

according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 5)

Clock In

(pin 6)

30 kΩ

20 kΩ

PHO

(pin 3)

Gain = V

/ 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International

•

166 Glover Avenue, Norwalk, CT 06856

•

Tel: 1-88-VECTRON-1• http://www.vectron.com

Recommended Resources

Touch lighting switch circuit four

AOC CM-312 color display power supply circuit diagram

Water level automatic control circuit

General connection method of AC welding machine

STK085-105 power amplifier circuit

Circuit diagram: voice control circuit

Mr. Nan Guo's "I Want to Be on the Spring Festival Gala": The annual Spring Festival is approaching. Celebrities and stars are becoming active. It is said that since the Qi State changed its king who loved to listen to solos, Mr. Nan Guo ran back home and ha...; 西门 Talking

What is the difference between AF_DISCV_ROUTE, AF_SKIP_ROUTING and AF_SUPRESS_ROUTE_DISC_NETWORK?: Hello everyone. In the AF_DataRequest function call of z-stack, there is an Options parameter, which is assigned one or more of the three values mentioned above. What I can understand now is that when...; Zigbee_App RF/Wirelessly

Graduation Project: A Simple Networking Experiment: I can't find where this program is and how to set it up. Thanks for your help....; 小小漫 RF/Wirelessly

STM32F207 and 103 are compared: Today I compared STM32F207 and 103. I want to make a compatible design between STM32F207 and 103. Both have 144Pin. It is really annoying to draw PCB! I will do it once, and it is better to make both ...; yoyu1358 stm32/stm8

Does anyone use makefile to batch process arm programs?: Recently, I often need to use Makefile to compile and link arm programs at work, but now I still can't get away from the integrated development environment. I hope experts can give me some advice. The...; 05210324kw MCU

Can the built-in FLASH of STM32 be used as a USB flash drive?: I found an article online titled " How to make a super small USB flash drive using STM32's built-in Flash in 5 minutes " but the method he provided doesn't work. Can the STM32 built-in FLASH be used a...; ldh2008 stm32/stm8

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components