2N3955
MONOLITHIC DUAL
N-CHANNEL JFET
The 2N3955 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The 2N3955 family are matched JFET pairs for
differential amplifiers. The 2N3955 family of general
purpose JFETs is characterized for low and medium
frequency differential amplifiers requiring low offset
voltage, drift, noise and capacitance
The 2N3955 family exhibits low capacitance - 6pF max
and a spot noise figure of - 0.5dB max. The part offers
a superior tracking ability.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
LOW LEAKAGE
LOW NOISE
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
|∆ V
GS1‐2
/∆T|= 5µV/°C max.
I
G
= 20pA TYP.
e
n
= 10nV/√Hz TYP.
2N3955 Applications:
Wideband Differential Amps
High Input Impedance Amplifiers
Maximum Temperatures
Storage Temperature
‐65°C to +200°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V
GSS
Gate Voltage to Drain or Source
60V
‐V
DSO
Drain to Source Voltage
60V
‐I
G(f)
Gate Forward Current
50mA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 400mW @ 25°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V
GS1‐2
/ T| max.
DRIFT VS.
25
µV/°C V
DG
=20V, I
D
=200µA
TEMPERATURE
T
A
=‐55°C to +125°C
| V
GS1‐2
| max.
OFFSET VOLTAGE
10
mV
V
DG
=20V, I
D
=200µA
MAX.
‐‐
‐‐
3000
1000
3
5
5
4.5
4
50
50
‐‐
100
5
1
0.1
‐‐
‐‐
0.5
15
6
2
‐‐
UNITS
V
V
µmho
µmho
%
mA
%
V
V
pA
nA
pA
pA
µmho
µmho
µmho
dB
dB
dB
nV/√Hz
pF
pF
pF
CONDITIONS
V
DS
= 0 I
D
=1µA
I
G
= 1nA I
D
= 0 I
S
= 0
V
DG
= 20V V
GS
= 0V f = 1kHz
V
DG
= 20V I
D
= 200µA
V
DG
= 20V V
GS
= 0V
V
DS
= 20V I
D
= 1nA
V
DS
=20V I
D
=200µA
V
DG
= 20V I
D
= 200µA
T
A
= +125°C
V
DG
= 10V I
D
= 200µA
V
DG
= 20V V
DS
= 0
V
DG
= 20V V
GS
= 0V
V
DG
= 20V I
D
= 200µA
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
TYP.
BV
GSS
Breakdown Voltage
60
‐‐
BV
GGO
Gate‐To‐Gate Breakdown
60
‐‐
TRANSCONDUCTANCE
Y
fSS
Full Conduction
1000
2000
Y
fS
Typical Operation
500
700
|Y
FS1‐2
/ Y
FS
|
Mismatch
‐‐
0.6
DRAIN CURRENT
I
DSS
Full Conduction
0.5
2
|I
DSS1‐2
/ I
DSS
|
Mismatch at Full Conduction
‐‐
1
GATE VOLTAGE
V
GS
(off) or V
p
Pinchoff voltage
1
2
V
GS
(on)
Operating Range
0.5
‐‐
GATE CURRENT
‐I
G
Operating
‐‐
20
‐I
G
High Temperature
‐‐
‐‐
‐I
G
Reduced V
DG
‐‐
5
‐I
GSS
At Full Conduction
‐‐
‐‐
OUTPUT CONDUCTANCE
Y
OSS
Full Conduction
‐‐
‐‐
Y
OS
Operating
‐‐
0.1
|Y
OS1‐2
|
Differential
‐‐
0.01
COMMON MODE REJECTION
CMR
‐20 log | V
GS1‐2
/ V
DS
|
‐‐
100
CMR
‐20 log | V
GS1‐2
/ V
DS
|
‐‐
75
NOISE
NF
Figure
‐‐
‐‐
e
n
Voltage
‐‐
‐‐
CAPACITANCE
C
ISS
Input
‐‐
‐‐
C
RSS
Reverse Transfer
‐‐
‐‐
C
DD
Drain‐to‐Drain
‐‐
0.1
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
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∆V
DS
= 10 to 20V I
D
=200µA
∆V
DS
= 5 to 10V I
D
=200µA
V
DS
= 20V V
GS
= 0V R
G
= 10MΩ
f= 100Hz NBW= 6Hz
V
DS
=20V I
D
=200µA f=10Hz NBW=1Hz
V
DS
= 20V V
GS
= 0V f= 1MHz
V
DG
= 20V I
D
= 200µA
PDIP / SOIC (Top View)
Available Packages:
2N3955 in PDIP / SOIC
2N3955 available as bare die
Please contact
Micross
for full package and die dimensions
Micross Components Europe
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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