LS5907
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
The LS5907 is a high-performance monolithic dual
JFET featuring tight matching and low drift over
temperature specifications, and is targeted for use in a
wide range of precision instrumentation applications
where tight tracking is required.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
ULTRA LOW LEAKAGE
LOW PINCHOFF
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
| V
GS1‐2
/ T| = 5µV/°C TYP.
I
G
= 150fA TYP.
V
p
= 2V TYP.
LS5907 Benefits:
Tight Tracking
Good matching
Ultra Low Leakage
Low Drift
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V
GSS
Gate Voltage to Drain or Source
40V
‐V
DSO
Drain to Source Voltage
40V
‐I
G(f)
Gate Forward Current
10mA
‐I
G
Gate Reverse Current
10µA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 40mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V
GS1‐2
/ T| max.
DRIFT VS.
10
µV/°C V
DG
=10V, I
D
=30µA
TEMPERATURE
T
A
=‐55°C to +125°C
| V
GS1‐2
| max.
OFFSET VOLTAGE
5
mV
V
DG
=10V, I
D
=30µA
TYP.
60
‐‐
300
100
1
400
2
2
‐‐
‐‐
‐‐
‐‐
‐‐
1
‐‐
0.1
0.01
90
90
‐‐
20
‐‐
‐‐
‐‐
MAX.
‐‐
‐‐
500
200
5
1000
5
4.5
4
1
1
2
5
‐‐
5
0.1
0.1
‐‐
‐‐
1
70
3
1.5
0.1
UNITS
V
V
µmho
µmho
%
µA
%
V
V
pA
nA
pA
nA
pA
µmho
CONDITIONS
V
DS
= 0 I
D
=1nA
I
G
= 1nA I
D
= 0 I
S
= 0
V
DG
= 10V V
GS
= 0V f = 1kHz
V
DG
= 10V I
D
= 30µA f = 1kHz
V
DG
= 10V V
GS
= 0V
V
DS
= 10V I
D
= 1nA
V
DS
=10V I
D
=30µA
V
DG
= 10V I
D
= 30µA
T
A
= +125°C
V
DS
=0V V
GS
= 20V
T
A
= +125°C
V
GG
= 20V
V
DG
= 10V V
GS
= 0V
V
DG
= 10V I
D
=30µA
∆V
DS
= 10 to 20V I
D
=30µA
∆V
DS
= 5 to 10V I
D
=30µA
V
DS
= 10V V
GS
= 0V R
G
= 10MΩ
f= 100Hz NBW= 6Hz
V
DG
=10V I
D
=30µA f=10Hz NBW=1Hz
V
DS
= 10V V
GS
= 0V f= 1MHz
V
DG
= 20V I
D
=30µA
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV
GSS
Breakdown Voltage
40
BV
GGO
Gate‐To‐Gate Breakdown
40
TRANSCONDUCTANCE
Y
fSS
Full Conduction
70
Y
fS
Typical Operation
50
|Y
FS1‐2
/ Y
FS
|
Mismatch
‐‐
DRAIN CURRENT
I
DSS
Full Conduction
60
|I
DSS1‐2
/ I
DSS
|
Mismatch at Full Conduction
‐‐
GATE VOLTAGE
V
GS
(off) or V
p
Pinchoff voltage
0.6
V
GS
(on)
Operating Range
‐‐
GATE CURRENT
‐I
G
max.
Operating
‐‐
‐I
G
max.
High Temperature
‐‐
‐I
GSS
max.
At Full Conduction
‐‐
‐I
GSS
max.
High Temperature
‐‐
I
GGO
Gate‐to‐Gate Leakage
‐‐
OUTPUT CONDUCTANCE
Y
OSS
Full Conduction
‐‐
Y
OS
Operating
‐‐
|Y
OS1‐2
|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log |∆V
GS1‐2
/∆V
DS
|
‐‐
CMR
‐20 log |∆V
GS1‐2
/∆V
DS
|
‐‐
NOISE
NF
Figure
‐‐
e
n
Voltage
‐‐
CAPACITANCE
C
ISS
Input
‐‐
C
RSS
Reverse Transfer
‐‐
C
DD
Drain‐to‐Drain
‐‐
Click To Buy
dB
dB
nV/√Hz
pF
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
SOIC / PDIP (Top View)
Available Packages:
LS5907 in PDIP / SOIC
LS5907 available as bare die
Please contact
Micross
for full package and die dimensions
Micross Components Europe
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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