LS843
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS843 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS843 features a 1-
mV offset and 5-µV/°C drift.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
| V
GS1‐2
/ T| ≤5µV/°C
LOW LEAKAGE
I
G
= 15pA TYP.
LOW NOISE
e
n
= 3nV/√Hz TYP.
LOW OFFSET VOLTAGE
| V
GS1‐2
| ≤1mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V
GSS
Gate Voltage to Drain or Source
60V
‐V
DSO
Drain to Source Voltage
60V
‐I
G(f)
Gate Forward Current
50mA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V
GS1‐2
/ T| max.
DRIFT VS.
5
µV/°C V
DG
=10V, I
D
=500µA
TEMPERATURE
T
A
=‐55°C to +125°C
| V
GS1‐2
| max.
OFFSET VOLTAGE
1
mV
V
DG
=10V, I
D=
500µA
MAX.
‐‐
‐‐
‐‐
‐‐
3
15
5
3.5
3.5
50
50
30
100
20
2
0.2
‐‐
‐‐
0.5
7
11
8
3
‐‐
UNITS
V
V
µmho
µmho
%
mA
%
V
V
pA
nA
pA
pA
µmho
µmho
µmho
dB
CONDITIONS
V
DS
= 0 I
D
=1nA
I
G
= 1nA I
D
= 0 I
S
= 0
V
DG
= 15V V
GS
= 0V f = 1kHz
V
DG
= 15V I
D
= 500µA
V
DG
= 15V V
GS
= 0V
V
DS
= 15V I
D
= 1nA
V
DS
=15V I
D
=500µA
V
DG
= 15V I
D
= 500µA
T
A
= +125°C
V
DG
= 3V I
D
= 500µA
V
DG
= 15V , V
DS
=0
V
DG
= 15V V
GS
= 0V
V
DG
= 15V I
D
= 500µA
LS843 Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
TYP.
BV
GSS
Breakdown Voltage
60
‐‐
BV
GGO
Gate‐To‐Gate Breakdown
60
‐‐
TRANSCONDUCTANCE
Y
fSS
Full Conduction
1500
‐‐
Y
fS
Typical Operation
1000
1500
|Y
FS1‐2
/ Y
FS
|
Mismatch
‐‐
0.6
DRAIN CURRENT
I
DSS
Full Conduction
1.5
5
|I
DSS1‐2
/ I
DSS
|
Mismatch at Full Conduction
‐‐
1
GATE VOLTAGE
V
GS
(off) or V
p
Pinchoff voltage
1
‐‐
V
GS
(on)
Operating Range
0.5
‐‐
GATE CURRENT
‐I
G
max.
Operating
‐‐
15
‐I
G
max.
High Temperature
‐‐
‐‐
‐I
G
max.
Reduced V
DG
‐‐
5
‐I
GSS
max.
At Full Conduction
‐‐
‐‐
OUTPUT CONDUCTANCE
Y
OSS
Full Conduction
‐‐
‐‐
Y
OS
Operating
‐‐
0.2
|Y
OS1‐2
|
Differential
‐‐
0.02
COMMON MODE REJECTION
CMR
‐20 log | V
GS1‐2
/ V
DS
|
90
110
‐20 log | V
GS1‐2
/ V
DS
|
‐‐
85
NOISE
NF
Figure
‐‐
‐‐
e
n
Voltage
‐‐
‐‐
‐‐
‐‐
CAPACITANCE
C
ISS
Input
‐‐
‐‐
C
RSS
Reverse Transfer
‐‐
‐‐
C
DD
Drain‐to‐Drain
‐‐
0.5
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
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dB
nV/√Hz
pF
∆V
DS
= 10 to 20V I
D
=500µA
∆V
DS
= 5 to 10V I
D
=500µA
V
DS
= 15V V
GS
= 0V R
G
= 10MΩ
f= 100Hz NBW= 6Hz
V
DS
=15V I
D
=500µA f=1KHz NBW=1Hz
V
DS
=15V I
D
=500µA f=10Hz NBW=1Hz
V
DS
= 15V, I
D
=500µA
V
DG
= 15V, I
D
=500µA
PDIP & SOIC (Top View)
Available Packages:
LS843 / LS843 in PDIP & SOIC
LS843 / LS843 available as bare die
Please contact
Micross
for full package and die dimensions
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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