Advanced Information
GS8180D09/18B-333/300/275/250
209-Bump BGA
Commercial Temp
Industrial Temp
Σ
RAM
2M x 9, 1M x 18
Separate I/O Sigma DDR SRAM
333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/
Features
• Double Data Rate Read and Write mode
• Observes the Sigma RAM pinout standard
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 user-programmable chip enable inputs for easy depth
expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin compatible with future 32M, 64M and 128M devices
- 333
3.0 ns
1.5 ns
Pipeline Mode
tKHKH
tKHQV
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
falling edges of clock and drives data on both clock edges as
well.
Because the Separate I/O DDR
ΣRAM
always transfers data in
four packets, A0 and A1 are internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Since the LSBs are tied off internally, the address
field of a Separate I/O DDR
ΣRAM
is always two address pins
less than the advertised index depth (e.g., the 1M x 18 has a
256K addressable index).
Single Data Rate (SDR) Separate I/O Sigma RAMs implement
a pipelined read and incorporate a rising-edge-triggered output
register. In DDR mode, rising- and falling-edge-triggered
output registers are employed. For read cycles, a DDR
SRAM’s output data is temporarily stored by the edge-
triggered output register during the access cycle, and then
released to the output drivers at the next rising and subsequent
falling edge of clock.
GS818x18/36B
ΣRAMs
are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
Sigma RAM Family Overview
The GS8180D09/18B are built in compliance with the Sigma
RAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (16Mb) SRAMs. These are the first in
a family of wide, very low voltage CMOS I/O SRAMs
designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's family of Common I/O
ΣRAMs
are offered in a number
of configurations that emulate other synchronous SRAMs,
such as Burst RAMs, NBT RAMs, Late Write, or Double Data
Rate (DDR) SRAMs. The logical differences between the
protocols employed by these RAMs hinge mainly on various
combinations of address bursting, output data registering, and
write cueing.
ΣRAMs
allow a user to implement the interface
protocol best suited to the task at hand.
Functional Description
Because a Sigma RAM is a synchronous device, address, and
read/ write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
Rev: 1.01 11/2000
1/33
© 2000, Giga Semiconductor, Inc.
A
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Advanced Information
GS8180D09/18B-333/300/275/250
8180D36 Pinout
512K x 36 Separate I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
•
2
Dc2
Dc4
Dc6
Dc8
Qc1
Qc2
Qc4
Qc6
Qc8
CQ2
Dd8
Dd6
Dd4
Dd2
Dd1
Qd8
Qd6
Qd4
Qd2
3
A
MCL
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
4
E2
NC
MCL
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
(16M)
6
MCL
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
MCL
MCL
7
A
(8M)
8
E3
MCL
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
NC
MCL
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
10
Qb1
Qb3
Qb5
Qb7
Db1
Db2
Db4
Db6
Db8
CQ1
Qa8
Qa6
Qa4
Qa2
Qa1
Da8
Da6
Da4
Da2
11
Qb2
Qb4
Qb6
Qb8
Qb9
Db3
Db5
Db7
Db9
CQ1
Qa9
Qa7
Qa5
Qa3
Da9
Da7
Da5
Da3
Da1
Dc1
Dc3
Dc5
Dc7
Dc9
Qc3
Qc5
Qc7
Qc9
CQ2
Dd9
Dd7
Dd5
Dd3
Qd9
Qd7
Qd5
Qd3
Qd1
A
NC
(128M)
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
A
A
TMS
TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch—MS-028vBC
Note:
Users of CMOS I/O Sigma RAMs may wish to connect D4, D8, T4, T8 and K4 to V
DDQ
/2 to allow alternate use of HSTL
I/O Sigma RAMs.
Rev: 1.01 11/2000
2/33
© 2000, Giga Semiconductor, Inc.
A
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Advanced Information
GS8180D09/18B-333/300/275/250
8180D18 Pinout
1M x 18 Separate I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
•
2
Db2
Db4
Db6
Db8
Qb1
Qb2
Qb4
Qb6
Qb8
CQ2
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
A
MCL
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
4
E2
NC
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
(16M)
6
MCL
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
MCL
MCL
7
A
(8M)
8
E3
NC
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
NC
MCL
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ1
Qa8
Qa6
Qa4
Qa2
Qa1
Da8
Da6
Da4
Da2
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ1
Qa9
Qa7
Qa5
Qa3
Da9
Da7
Da5
Da3
Da1
Db1
Db3
Db5
Db7
Db9
Qb3
Qb5
Qb7
Qb9
CQ2
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
NC
(128M)
A
A
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
A
A
TMS
TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch—MS-028vBC
Note:
Users of CMOS I/O Sigma RAMs may wish to connect D4, D8, T4, T8 and K4 to V
DDQ
/2 to allow alternate use of HSTL
I/O Sigma RAMs.
Rev: 1.01 11/2000
3/33
© 2000, Giga Semiconductor, Inc.
A
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Advanced Information
GS8180D09/18B-333/300/275/250
8180D09 Pinout
2M x 9 Separate I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 1
•
2
D2
D4
D6
D8
Q1
Q2
Q4
Q6
Q8
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
A
NC
NC
4
E2
NC
NC
5
A,
NC
(16M)
A
(x36)
A,
NC
(128M)
6
MCL
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
MCL
MCL
7
A,
NC
(8M)
A
A
(x18)
8
E3
NC
A
(x9)
9
A
NC
NC
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D1
D3
D5
D7
D9
Q3
Q5
Q7
Q9
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
A
A
A
A
TMS
TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch—MS-028vBC
Note:
Users of CMOS I/O Sigma RAMs may wish to connect D4, D8, T4, T8 and K4 to V
DDQ
/2 to allow alternate use of HSTL
I/O Sigma RAMs.
Rev: 1.01 11/2000
4/33
© 2000, Giga Semiconductor, Inc.
A
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Advanced Information
GS8180D09/18B-333/300/275/250
Pin Description Table
Pin Location
A3, A5, A7, A9, B5, B7,
U4, U6, U8, V3, V4, V5,
V6, V7, V8, V9, W5, W7
C7
C5, C8
K3
K1
K11
K2
K10
C6
A4, A8
G6, H6
W9
W4
W8
W3
L6, M6, J6
N6
A6, D6, K6, P6, T6, W6
B3, C9
B8, C4
Symbol
A
A
A
CK
CQ
CQ
CQ
CQ
DQ
E1
E2 & E3
EP2 & EP3
G
TCK
TDI
TDO
TMS
M2, M3 & M4
MCH
MCL
MCL
MCL
Description
Address
Address
Address
Clock
Echo Clock
Echo Clock
Echo Clock
Echo Clock
Data I/O
Chip Enable
Chip Enable
Chip Enable Program Pin
Asynchronous Output Enable
Test Clock
Test Data In
Test Data Out
Test Mode Select
Mode Control Pins
Must Connect High
Must Connect Low
Must Connect Low
Must Connect Low
Type
Input
Input
Input
Input
Output
Output
Output
Output
Input/Output
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Comments
(all versions)
(x09 and x18 versions)
(x09 version only)
Active High
Active High
Active High (x18 and x36 versions)
Active Low
Active Low (x18 and x36 versions)
—
Active Low
Programmable Active High or Low
—
Active Low
Active High
—
—
—
—
Active High
Active Low (all versions)
Active Low (x18 and x36 versions)
Active Low (x36 version only)
Rev: 1.01 11/2000
5/33
© 2000, Giga Semiconductor, Inc.
A
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
京公网安备 11010802033920号
EEWORLD
