Operating Temperature Range ......................... -40°C to +125°C
Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (soldering, 10s) ................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
4 SOT23
PACKAGE CODE
U4+1/U4+1A
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board
Junction to Ambient (q
JA
)
Junction to Case (q
JC
)
Thermal Resistance, Four-Layer Board
Junction to Ambient (q
JA
)
Junction to Case (q
JC
)
21-0052
90-0183
N/A
N/A
290
100
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that
a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial
.
www.maximintegrated.com
Maxim Integrated │ 2
MAX6394
High-Accuracy μP Reset Circuit
Electrical Characteristics
PARAMETER
Operating Voltage Range
(V
CC
= +2.4V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
SYMBOL
V
CC
CONDITIONS
T
A
= -40°C to +125°C
V
CC
= 5.5V, no load (-40°C to +85°C)
V
CC
Supply Current
I
CC
V
CC
= 5.5V, no load (-40°C to +125°C)
V
CC
= 3.6V, no load (-40°C to +85°C)
V
CC
= 3.6V, no load (-40°C to +125°C)
Reset Threshold (Note 1)
V
TH
∆V
TH
/°C
V
CC
= falling at 1mV/µs
MAX6394US_ _ _D1+T
Reset Timeout Period
t
RP
MAX6394US_ _ _D2-T
MAX6394US_ _ _D3-T
MAX6394US_ _ _D4-T
MANUAL RESET INPUT
V
IL
MR
Input Threshold
V
IH
V
IL
V
IH
MR
Minimum Input Pulse
MR
Glitch Rejection
MR
to Reset Delay
MR
Pullup Resistance
V
CC
> 4.25V, I
SINK
= 3.2mA
RESET
Output Voltage
V
OL
V
CC
> 2.5V, I
SINK
= 1.2mA
V
CC
> 1.2V, I
SINK
= 0.5mA
V
CC
> 1.0V, I
SINK
= 80µA
RESET
Output Leakage Current
V
CC
> VTH,
RESET
deasserted
32
1
100
500
63
100
0.4
0.3
0.3
0.3
1
µA
V
V
TH
< 4.0V
0.3 x V
CC
0.7 x V
CC
µs
ns
ns
kΩ
V
TH
> 4.0V
0.8
2.4
V
0.7
14
105
826
T
A
= +25°C (see Table 1)
T
A
= -40°C to +125°C (see Table 2)
V
TH
-
0.6%
V
TH
-
1.0%
60
35
1.4
28
200
1570
2.0
40
280
2240
ms
V
TH
4
MIN
1.0
5
TYP
MAX
5.5
12
15
10
12
V
TH
+
0.6%
V
TH
+
1.0%
µA
UNITS
V
V
Reset Threshold Tempco
V
CC
to Reset Delay
ppm/°C
µs
Note 1:
The MAX6394 monitors V
CC
through an internal factory-trimmed voltage-divider that programs the nominal reset threshold.
Other thresholds may be available. Contact factory for availability.
www.maximintegrated.com
Maxim Integrated │
3
MAX6394
High-Accuracy μP Reset Circuit
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6394 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX6394 toc01
5
SUPPLY CURRENT (µA)
4
3
2
1
0
V
CC
= 1V
V
CC
= 5V
5
SUPPLY CURRENT (µA)
4
3
2
1
0
T
A
= +25°C
T
A
= -40°C
T
A
= +85°C
POWER-DOWN RESET DELAY (µs)
V
CC
FALLING AT 1mV/µs
40
30
20
10
0
V
TH
= 4.63V
V
TH
= 3.00V
V
CC
= 3V
-50
-30
-10
10
30
50
70
90
0
1
2
3
4
5
-50
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
MAX6394 toc04
MAX6394 toc05
NORMALIZED RESET TIMEOUT PERIOD
NORMALIZED RESET THRESHOLD
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
-50
-30
-10
10
30
50
70
1.004
1.002
1.000
0.998
0.996
0.994
MAXIMUM TRANSIENT DURATION (µs)
80
60
40
20
V
T
= 3.00V
0
10
100
V
TH
= 4.63V
T
A
= +25°C
RESET OCCURS
ABOVE CURVE
90
-50
-30
-10
10
30
50
70
90
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET COMP. OVERDRIVE, V
TH
- V
CC
(mV)
Pin Description
PIN
1
2
3
4
NAME
GND
RESET
MR
VCC
Ground
Active-Low Open-Drain Output. Connect to an external pullup resistor. Can be pulled up to a voltage higher
than V
CC
, but less than 6V.
Manual Reset Input. A logic-low on
MR
asserts reset. Reset remains asserted as long as
MR
is low, and for
the reset timeout period (t
RP
) after the reset conditions are terminated. Connect to VCC if not used.
Supply Voltage and Reset Threshold Monitor Input
FUNCTION
www.maximintegrated.com
Maxim Integrated │
4
MAX6394 toc06
1.04
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE (V
CC
RISING)
1.006
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE (V
CC
FALLING)
100
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
MAX6394 toc03
6
6
50
POWER-DOWN RESET DELAY
vs. TEMPERATURE
MAX6394
High-Accuracy μP Reset Circuit
Detailed Description
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in
a known state. The MAX6394 asserts a reset signal to
prevent code-execution errors during power-up, power-
down, or brownout conditions.
RESET
is guaranteed to be
a logic-low for V
CC
> 1V (see the
Electrical Characteristics
table). Once V
CC
exceeds the reset threshold, the internal
timer keeps
RESET
asserted for the reset timeout period
(t
RP
); after this interval
RESET
goes high. If a brownout
condition occurs (monitored voltage dips below its pro-
grammed reset threshold),
RESET
goes low. Any time
V
CC
dips below the reset threshold, the internal timer
resets to zero and
RESET
goes low. The internal timer
starts when V
CC
returns above the reset threshold, and
RESET
remains low for the reset timeout period.
The MAX6394’s
RESET
output structure is a simple open-
drain n-channel MOSFET switch. Connect a pullup resis-
tor to any supply in the 0 to +6V range. Select a resistor
value large enough to register a logic-low when
RESET
is asserted (see the
Electrical Characteristics
table), and
small enough to register a logic-high while supplying all
input current and leakage paths connected to the
RESET
line. A 10kΩ pullup is sufficient in most applications.
Often, the pullup connected to the MAX6394’s
RESET
output connects to the supply voltage monitored at the
IC’s VCC pin. However, some systems may use the open-
drain output to level-shift from the monitored supply to
reset circuitry powered by some other supply (Figure 1).
This is one useful feature of an open-drain output. Keep in
mind that as the MAX6394’s V
CC
decreases below 1V, so
does the IC’s ability to sink current at
RESET.
Finally, with
any pullup,
RESET
is pulled high as V
CC
decays toward
0V. The voltage where this occurs depends on the pullup
resistor value and the voltage to which it connects (see the
Electrical Characteristics
table).
+3.3V
VCC
10kΩ
MR
RESET
+5.0V
5V SYSTEM
MAX6394
GND
Figure 1. MAX6394 Open-Drain
RESET
Output Allows Use
with Multiple Supplies
switch from
MR
to GND to create a manual reset function;
external debounce circuitry is not required. If
MR
is driven
from long cables or if the device is used in a noisy environ-
ment, connecting a 0.1μF capacitor from
MR
to ground
provides additional noise immunity.
Applications Information
Negative-Going V
CC
Transients
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration negative-going
transients (glitches). The
Typical Operating Characteristics
show the Maximum Transient Duration vs. Reset Threshold
Overdrive, for which reset pulses are not generated. The
graph was produced using negative-going pulses, starting
at VRST max and ending below the programmed reset
threshold by the magnitude indicated (reset threshold
overdrive). The graph shows the maximum pulse width
that a negative-going V
CC
transient may typically have
without causing a reset pulse to be issued. As the transient
amplitude increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width decreases.
A 0.1μF bypass capacitor mounted close to VCC provides
additional transient immunity.
Manual-Reset Input
Many μP-based products require manual-reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. A logic-low on
MR
asserts reset.
RESET
remains asserted while
MR
is low, and for the
reset active timeout period after
MR
returns high.
MR
has an internal 63kΩ pullup resistor, so it can be left
open if not used. Connect a normally open momentary
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