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Datasheet> All Categories > storage> storage> GS840FH32AT-7.5IT
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GS840FH32AT-7.5IT

Description
Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size792KB，22 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
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GS840FH32AT-7.5IT Overview

Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100

GS840FH32AT-7.5IT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time7.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)113 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
length20 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM
memory width32
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.03 A
Minimum standby current3.14 V
Maximum slew rate0.125 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm

GS840FH32AT-7.5IT Preview

Preliminary
GS840FH18/32/36AT-7.5/8/8.5/10/12
TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP
-7.5
7.5
8.8
115
-8
8
9.1
115
-8.5
8.5
10
105
-10
10
10
105
-12
12
15
80
Unit
ns
ns
mA
ns–12
256K x 18, 128K x 32, 128K x 36
7.5 3.3 V Vns
DD
4Mb Sync Burst SRAMs
3.3 V and 2.5 V I/O
Designing For Compatibility
The JEDEC standard for Burst RAMs calls for a FT mode pin
option (Pin 14 on TQFP). Board sites for flow through Burst
RAMs should be designed with V
SS
connected to the FT pin
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s pipeline/flow through-configurable Burst
RAMs or any vendor’s flow through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable flow through Burst
RAM, (e.g., GS840FH18/32/36A), to achieve flow through
functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Flow
t
KQ
Through tCycle
2-1-1-1
I
DD
Functional Description
Applications
The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840FH18/32/36A is
available in a JEDEC-standard 100-lead TQFP package.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS840FH18/32/36A operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V
DDQ
) pins are used to decouple
output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.04 3/2001
1/22
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS840FH18/32/36AT-7.5/8/8.5/10/12
GS840FH18A 100-Pin TQFP Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
NC
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
17
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
Rev: 1.04 3/2001
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
2/22
© 1999, Giga Semiconductor, Inc.
.
Preliminary
GS840FH18/32/36AT-7.5/8/8.5/10/12
GS840FH32A 100-Pin TQFP Pinout
NC
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
NC
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
NC
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
NC
Rev: 1.04 3/2001
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3/22
© 1999, Giga Semiconductor, Inc.
.
Preliminary
GS840FH18/32/36AT-7.5/8/8.5/10/12
GS840FH36A 100-Pin TQFP Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
NC
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
Rev: 1.04 3/2001
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
4/22
© 1999, Giga Semiconductor, Inc.
.
Preliminary
GS840FH18/32/36AT-7.5/8/8.5/10/12
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
80
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
87
93, 94
95, 96
95, 96
89
88
98, 92
97
86
83
84, 85
64
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
14, 16, 38, 39, 42, 43, 66
Symbol
A
0
, A
1
A
2
–A
16
A
17
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
NC
DQ
A1
–DQ
A9
DQ
B1
-–DQ
B98
NC
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins. (x32, x36 Version)
I/O
—
I/O
Data Input and Output pins. (x36 Version)
No Connect (x32 Version)
Data Input and Output pins. (x18 Version)
—
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
—
No Connect (x18 Version)
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/O’s; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/O’s; active low
(x32, x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.04 3/2001
5/22
© 1999, Giga Semiconductor, Inc.
.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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GS840FH32AT-7.5IT Related Products

GS840FH32AT-7.5IT GS840FH18AT-7.5I GS840FH18AT-7.5T GS840FH18AT-7.5 GS840FH18AT-7.5IT GS840FH32AT-7.5I GS840FH32AT-7.5T GS840FH32AT-7.5 GS840FH36AT-7.5 GS840FH36AT-7.5T
Description Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX36, 7.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX36, 7.5ns, CMOS, PQFP100, TQFP-100
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology
Parts packaging code QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP
package instruction LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87
Contacts 100 100 100 100 100 100 100 100 100 100
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant compli
ECCN code 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B
Maximum access time 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns
Other features FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK) 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz 113 MHz
I/O type COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 code R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
length 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm
memory density 4194304 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4194304 bit 4194304 bit 4194304 bit 4718592 bit 4718592 bi
Memory IC Type CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
memory width 32 18 18 18 18 32 32 32 36 36
Humidity sensitivity level 3 3 3 3 3 3 3 3 3 3
Number of functions 1 1 1 1 1 1 1 1 1 1
Number of terminals 100 100 100 100 100 100 100 100 100 100
word count 131072 words 262144 words 262144 words 262144 words 262144 words 131072 words 131072 words 131072 words 131072 words 131072 words
character code 128000 256000 256000 256000 256000 128000 128000 128000 128000 128000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 70 °C 70 °C 85 °C 85 °C 70 °C 70 °C 70 °C 70 °C
organize 128KX32 256KX18 256KX18 256KX18 256KX18 128KX32 128KX32 128KX32 128KX36 128KX36
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP
Encapsulate equivalent code QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
power supply 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Maximum standby current 0.03 A 0.03 A 0.02 A 0.02 A 0.03 A 0.03 A 0.02 A 0.02 A 0.02 A 0.02 A
Minimum standby current 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
Maximum slew rate 0.125 mA 0.125 mA 0.115 mA 0.115 mA 0.125 mA 0.125 mA 0.115 mA 0.115 mA 0.115 mA 0.115 mA
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
width 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
JESD-609 code - - e0 e0 - - e0 e0 e0 e0
Terminal surface - - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)

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I would like to ask if anyone has used IQmath with 28035 successfully?
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TI DSP fixed-point arithmetic operation one
[i=s]This post was last edited by fish001 on 2017-9-23 18:30[/i] [p=28, null, left][color=#000000]In fixed-point DSP chips, fixed-point numbers are used for numerical calculations, and their operands ...
fish001 DSP and ARM Processors
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