Preliminary
GS8150Z18/36T-225/200/180/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
-225 -200 -180
2.5 3.0 3.2
Pipeline
t
KQ
4.4 5.0 5.5
3-1-1-1
tCycle
Curr (x18) 350 315 290
Curr (x36) 410 370 340
7.0 7.5
8
Flow
t
KQ
Through
8.5 10 10
tCycle
2-1-1-1 Curr (x18) 205 185 185
Curr (x36) 240 210 210
-166 -150 -133 Unit
3.5 3.8 4.0 ns
6.0 6.6 7.5 ns
270 250 230 mA
315 290 260 mA
8.5
10
185
210
10 11
10 15
185 140
210 160
ns
ns
mA
mA
16Mb Pipelined and Flow Through
225 MHz–133 MHz
3.3 V V
DD
Synchronous NBT SRAM
2.5 V or 3.3 V I/O
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8150Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8150Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Functional Description
The GS8150Z18/36T is a 16Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
Read/Write
A
R
B
W
Q
A
C
R
D
B
Q
A
1/24
D
W
Q
C
D
B
E
R
D
D
Q
C
F
W
Q
E
D
D
Q
E
Flow Through
Data I/O
Pipelined
Data I/O
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8150Z18/36T-225/200/180/166/150/133
GS8150Z18T Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
V
DD
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
18
A
17
A
8
A
9
A
19
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
Rev: 1.01 11/2000
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
2/24
© 2000, Giga Semiconductor, Inc.
Preliminary
GS8150Z18/36T-225/200/180/166/150/133
GS8150Z36T Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
V
DD
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
18
A
17
A
8
A
9
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
Rev: 1.01 11/2000
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3/24
© 2000, Giga Semiconductor, Inc.
Preliminary
GS8150Z18/36T-225/200/180/166/150/133
100-Pin TQFP Pin Descriptions
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 84, 83,
82, 81, 44, 45, 46,47, 48, 49, 50
80
89
93
94
95
96
88
98
97
92
86
85
87
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30
68, 69, 72, 73, 74, 75,
78, 79, 80
1, 2, 3, 6, 7, 8, 9, 12, 13
64
14
31
15, 16, 41, 65, 91
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
38, 39, 42, 43, 66
Symbol
A
0
, A
1
A
2
–A
18
A
19
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
DQ
B1
–DQ
B9
NC
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
—
I/O
I/O
I/O
I/O
In
In
In
In
In
In
—
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low (x36 Versions Only)
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low (x36 Versions Only)
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
No Connect (x18 Version Only)
Byte A Data Input and Output pins (x36 Versions Only)
Byte B Data Input and Output pins (x36 Versions Only)
Byte C Data Input and Output pins (x36 Versions Only)
Byte D Data Input and Output pins (x36 Versions Only)
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
3.3 V power supply
Ground
3.3 V output power supply for noise reduction
No Connect
58, 59, 62,63, 68, 69, 72, 73, 74 DQ
A1
–DQ
A9
51, 52, 53, 56, 57, 58, 59, 62,63 DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
–DQ
D9
Rev: 1.01 11/2000
4/24
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8150Z18/36T-225/200/180/166/150/133
GS8150Z18/36 NBT SRAM Functional Block Diagram
DQa
–
DQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst
Counter
K
Register 2
SA1’
SA0’
Read, Write and
Data Coherency
D
K
K
Control Logic
SA1
SA0
K
Write Address
Register 1
Match
Q
A
0
–An
LBO
W
K
FT
B
A
B
B
E
1
E
2
ADV
E
3
CK
Rev: 1.01 11/2000
5/24
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CKE
B
C
B
D
G
Write Drivers
Memory
Array
Register 2
K
Sense Amps
K
京公网安备 11010802033920号
EEWORLD
