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Datasheet> All Categories > storage> storage> GS8151E36T-150I
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GS8151E36T-150I

Description
Standard SRAM, 512KX36, 10ns, CMOS, PQFP100
Categorystorage    storage   
File Size578KB，31 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS8151E36T-150I Overview

Standard SRAM, 512KX36, 10ns, CMOS, PQFP100

GS8151E36T-150I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerGSI Technology
package instructionQFP, QFP100,.63X.87
Reach Compliance Codecompliant
Maximum access time10 ns
Maximum clock frequency (fCLK)150 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
memory density18874368 bit
Memory IC TypeSTANDARD SRAM
memory width36
Humidity sensitivity level3
Number of terminals100
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature-40 °C
organize512KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum standby current0.02 A
Minimum standby current3.14 V
Maximum slew rate0.25 mA
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationQUAD

GS8151E36T-150I Preview

Preliminary
GS8151E18/36T-225/200/180/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline opera-
tion
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-225
4.4
2.5
205
240
7.0
8.5
350
410
-200
5.0
3.0
185
210
7.5
10.0
315
370
-180
5.5
3.2
185
210
8.0
10.0
290
340
-166
6.0
3.5
185
210
8.5
10.0
270
315
-150
6.6
3.8
185
210
10.0
10.0
250
290
-133
7.5
4.0
140
160
11.0
15.0
230
260
Unit
ns
ns
mA
mA
ns
ns
mA
mA
1M x 18, 512K x 36
16Mb Sync Burst SRAMs
Flow Through/Pipeline Reads
225 MHz–133 MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8151E18/36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Flow
tCycle
Through
t
KQ
2-1-1-1 Curr (x18)
Curr (x36)
Pipeline
t
KQ
3-1-1-1
tCycle
Curr (x18)
Curr (x36)
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
ByteSafe™ Parity Functions
The GS8151E18/36 features ByteSafe data security functions.
See detailed discussion following.
Functional Description
Applications
The GS8151E18/36T is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8151E18/36T operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V- and 2.5 V-compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Rev: 1.01 11/2000
1/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS8151E18/36T-225/200/180/166/150/133
GS8151E18 100-Pin TQFP Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
DP
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M X 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
A
18
NC
NC
B
B
B
A
A
17
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
19
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
QE
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
LBO
A
5
A
4
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
1
A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
A
10
A
11
A
12
A
13
A
14
A
15
A
16
2/31
© 1999, Giga Semiconductor, Inc.
A
3
A
2
Preliminary
GS8151E18/36T-225/200/180/166/150/133
GS8151E36 100-Pin TQFP Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
DP
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
A
18
B
D
B
C
B
B
B
A
A
17
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
QE
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
A
3
A
2
A
1
A
0
TMS
TDI
V
SS
V
DD
3/31
LBO
A
5
A
4
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDO
TCK
A
10
A
11
A
12
A
13
A
14
A
15
A
16
© 1999, Giga Semiconductor, Inc.
Preliminary
GS8151E18/36T-225/200/180/166/150/133
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92, 97
80
63, 62, 59, 58, 57, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7,
25, 28, 29, 30
16
66
87
93, 94
95, 96
95, 96
89
88
98
86
83
84, 85
64
38
39
42
43
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
Rev: 1.01 11/2000
Symbol
A
0
, A
1
A
2
–A
18
A
19
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
NC
DP
QE
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
G
ADV
ADSP, ADSC
ZZ
TMS
TDI
TDO
TCK
FT
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins (x36 Version)
I/O
I/O
Data Input and Output pins (x36 Version)
Data Input and Output pins (x18 Version)
—
I
O
I
I
I
—
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
4/31
No Connect (x18 Version)
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
(x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8151E18/36T-225/200/180/166/150/133
GS8151E18/36 Block Diagram
Register
A0
–
An
D
Q
A0
D0
A1
D1
Q1
Counter
Load
A
Q0
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
36
D
36
Register
D
B
B
Q
4
4
Register
D
B
C
Q
Register
D
Q
Register
Register
4
D
B
D
Q
Register
36
36
36
D
Q
Register
E
1
D
Q
32
Parity
Encode
4
Parity
Compare
36
36
Register
D
Q
FT
G
Power Down
Control
0
ZZ
DQx0
–
DQx9
QE
D
DP
Note: Only x36 version shown for simplicity.
Rev: 1.01 11/2000
5/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q
Q
D
Register
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Shortcut:   00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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