Freescale Semiconductor
Technical Data
Document Number: MC33882
Rev. 7.0, 3/2011
Six Output Low Side Switch with
SPI and Parallel Input Control
The 33882 is a smart six output low side switch able to control
system loads up to 1.0 A. The six outputs can be controlled via both
serial peripheral interface (SPI) and parallel input control, making the
device attractive for fault-tolerant system applications. There are two
additional 30 mA low side switches with SPI diagnostic reporting (with
parallel input control only).
The 33882 is designed to interface directly with industry standard
microcontrollers via SPI to control both inductive and incandescent
loads. Outputs are configured as open-drain power MOSFETs
incorporating internal dynamic clamping and current limiting. The
device has multiple monitoring and protection features, including low
standby current, fault status reporting, internal 52 V clamp on each
output, output specific diagnostics, and protective shutdown. In
addition, it has a mode select pin affording a dual means of input
control.
Features
•
•
•
•
•
•
•
•
Outputs clamped for switching inductive loads
Very low operational bias currents (< 2.0 mA)
CMOS input logic compatible with 5.0 V logic levels
Load dump robust (60 V transient at V
PWR
on OUT0 – OUT5)
Daisy chain operation of multiple devices possible
Switch outputs can be paralleled for higher currents
R
DS(ON)
of 0.4
Ω
per output (25 °C) at 13 V V
PWR
SPI operation guaranteed to 2.0 MHz
V
DD
Device
MC33882PVW/R2
MC33882PEP/R2
PC33882EK/R2
33882
SIX OUTPUT LOW SIDE SWITCH
VW SUFFIX
(PB-FREE)
98ASH70693A
30-PIN HSOP
EP SUFFIX
(PB-FREE)
98ARH99032A
32-PIN QFN
EK SUFFIX
(PB-FREE)
98ARL10543D
32-PIN SOIC
ORDERING INFORMATION
Temperature
Range (T
A
)
Package
30 HSOP
-40 to 125 °C
32 QFN
32 SOIC-EP
V
PWR
33882
VPWR
VDD
CS
SCLK
SI
SO
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUT0
OUT1
OUT3
OUT4
OUT5
OUT6
OUT7
IN0 & IN1
IN2 & IN3
IN4 & IN5
MODE
GND
Optional Control
of Paired Outputs
Low Power
LED
Outputs
High Power
Outputs
MCU
Optional Parallel
Control of
Outputs 0 through 7
Figure 1. 33882 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 -2011. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
1 (VPWR)
12 (SI)
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
On Open
16 (VDD)
V DD
Over-voltage
Shutdown
Under-voltage
Shutdown
Internal
Bias
3 (MODE)
18 (IN7)
29 (IN6)
27 (IN5)
24 (IN4)
28 (IN4 & IN5)
21 (IN3)
9 (IN2)
19 (IN2 & IN3)
Detect
Logic
Gate 7
Gate 6
Gate 5
Gate 4
Gate 3
Gate 2
Gate 0
OUT6
and OUT7
Unclamped
Low
Power
17
(OUT7)
30 (OUT6)
26 (OUT5)
OUT1
to OUT5
High
Power
23 (OUT4)
20 (OUT3)
10 (OUT2)
7 (OUT1)
5 (OUT0)
52 V
Gate 0
6 (IN1)
4 (IN0)
2 (IN0 & IN1)
Serial In
13 (SCLK)
0
1
2
3
4
5
6
7
SO Fault Latch/Shift Register
Output 0 Status
Output Status
1 through 7
Serial Out
V REF
I LIM
V DD
OFF/ON
Open
Load
Detect
V OF (th)
3.0 V
I O(OFF)
40
μA
+-
GND (Heat Sink)
-+
14 (CS)
Tri-state
15 (SO)
Shift
Enable
3.0 A
Load
Short
Detect
-+
Note
Pin numbers shown in this figure are applicable only to the 30-lead HSOP package.
Figure 2. 33882 Simplified Internal Block Diagram
33882
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
TRANSPARENT TOP VIEW
TRANSPARENT TOP VIEW
IN2&IN3
26
OUT5
OUT4
OUT3
27
IN5
IN4
IN3
VPWR
IN0&IN1
IN0
OUT0
IN1
OUT1
NC
IN2
OUT2
NC
SI
SCLK
SO
32
31
30
29
28
GND
HEATSINK
IN4&IN5
IN6
OUT6
GND
GND
VPWR
IN0&IN1
MODE
25
MODE
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT6
IN6
IN4&IN5
IN5
OUT5
NC
IN4
OUT4
NC
IN3
OUT3
IN2&IN3
IN7
OUT7
VDD
IN7
1
2
3
4
5
6
7
8
10
12
13
14
15
16
11
9
24
23
22
21
OUT7
VDD
GND
GND
GND
GND
SO
CS
HEATSINK
20
19
18
17
30 PIN HSOP
TRANSPARENT TOP VIEW
GND
NC
VDD
OUT7
IN7
IN2&IN3
OUT3
IN3
OUT4
IN4
OUT5
IN5
IN4&IN5
IN6
OUT6
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OUT0
OUT1
OUT2
HEATSINK
GND
NC
SO
CS
SCLK
SI
OUT2
IN2
OUT1
IN1
OUT0
IN0
MODE
IN0&IN1
VPWR
GND
32 PIN QFN
32 PIN SOIC
Figure 3. HSOP, QFN, and SOIC Pin Connections
Table 1. HSOP Pin Function Description
30 Pin
HSOP
1
2
19
28
32 Pin
QFN
6
7
26
1
32 Pin
SOIC
18
19
6
13
Pin Name
VPWR
IN0 & IN1
IN2 & IN3
IN4 & IN5
Formal Name
Load Supply Voltage
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
Definition
This pin is connected to battery voltage. A decoupling cap is required from
VPWR to ground.
These input pins control two output channels each when the
MODE
pin is
pulled high. These pins may be connected to pulse width modulated (PWM)
outputs of the control IC while the
MODE
pin is high. The states of these pins
are ignored during normal operation (
MODE
pin low), and override the
normal inputs (serial or parallel) when the
MODE
pin is high. These pins
have internal active 25
μA
pull-downs.
The
MODE
pin is connected to the
MODE
pin of the control IC. This pin has
an internal active 25
μA
pull-up.
3
8
20
MODE
Mode Select
33882
3
Analog Integrated Circuit Device Data
Freescale Semiconductor
SCLK
IN0
IN1
IN2
SI
PIN CONNECTIONS
Table 1. HSOP Pin Function Description (continued)
30 Pin
HSOP
4
6
9
18
21
24
27
29
5
7
10
17
20
23
26
30
8, 11, 22,
25
12
15
32 Pin
QFN
9
11
13
25
28
30
32
2
10
12
14
24
27
29
31
3
32 Pin
SOIC
21
23
25
5
8
10
12
14
22
24
26
4
7
9
11
15
2,31
27
Pin Name
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
NC
SI
Formal Name
Input 0 – Input7
Definition
These are parallel control input pins. These pins have internal 25
μA
active
pull-downs.
Output 0 – Output7
Each pin is one channel's drain, sinking current for the respective load.
No Connect
Serial Input
Not connected.
The Serial Input pin is connected to the SPI Serial Data Output pin of the
control IC from where it receives output command data. This input has an
internal active 25
μA
pull-down and requires CMOS logic levels.
The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It
transitions one time per bit transferred when in operation. It is idle between
command transfers. It is 50% duty cycle, and has CMOS levels.
This pin is connected to a chip select output of the control IC. This input has
an internal active 25
μA
pull-up and requires CMOS logic levels.
This pin is connected to the SPI Serial Data Input pin of the control IC or to
the SI pin of the next device in a daisy chain. This output will remain tri-
stated unless the device is selected by a low
CS
pin or the
MODE
pin goes
low. The output signal generated will have CMOS logic levels and the output
data will transition on the falling edges of SCLK. The serial output data
provides fault information for each output and is returned MSB first when the
device is addressed.
This pin is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from VDD to ground.
Ground continuity is required for the outputs to turn on. The heatsink must
be electrically connected to GND.
13
16
28
SCLK
Serial Clock
14
15
17
18
29
30
CS
SO
Chip Select
Serial Output
16
23
3
VDD
GND
Logic Supply Voltage
Ground
Heat
4,5,19- 1,16,17,
Sink
22
32
(exposed
pad)
(1)
Notes
1. The exposed pad on this package provides the circuit ground connection for the IC.
33882
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
ELECTRICAL RATINGS
Load Supply Voltage
Normal Operation (Steady-state)
Transient Survival
(2)
Logic Supply Voltage
(3)
Input Pin Voltage
(4)
Output Clamp Voltage (OUT0 to OUT5)
(5)
20 mA = I
O
= 0.2 A
Output Self-limit Current
OUT0 to OUT5
OUT6 and OUT7
ESD Voltage (HSOP, QFN, and SOIC)
Human Body Model
(6)
Machine Model
(7)
Output Clamp Energy
(8)
OUT0 to OUT5: Single Pulse at 1.5 A, T
J
= 150°C
OUT6 and OUT7: Single Pulse at 0.45 A, T
J
= 150°C
Maximum Operating Frequency (SPI) SO
(9)
THERMAL RATINGS
Storage Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow
(10)
,
(11)
Notes
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
T
STG
T
J
T
PPRT
-55 to 150
-40 to 150
Note 11
°C
°C
°C
f
OF
V
ESD1
V
ESD2
E
CLAMP
100
50
3.2
MHz
±2000
±200
mJ
I
O(LIM)
3.0 to 6.0
0.05 to 0.15
V
V
PWR(SS)
V
PWR(T)
V
DD
V
IN
V
O(OFF)
48 to 64
A
25
-1.5 to 60
-0.3 to 7.0
-0.3 to V
DD
+ 0.3
V
V
V
V
Symbol
Value
Limit
Transient capability with external 100
Ω
resistor in series with the VPWR pin and supply.
Exceeding these voltages may cause a malfunction or permanent damage to the device.
Exceeding the limits on any parallel inputs or SPI pins may cause permanent damage to the device.
With output OFF.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω).
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
Maximum output clamp energy capability at indicated junction temperature using a single pulse method.
Serial Frequency Specifications assume the IC is driving 8 tri-stated devices (20 pF each).
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
