74LVTN16245B
3.3 V 16-bit transceiver; 3-state
Rev. 3 — 15 June 2011
Product data sheet
1. General description
The 74LVTN16245B is a high-performance BiCMOS product designed for V
CC
operation
at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (nOE) for easy
cascading and a direction input (nDIR) for direction control.
2. Features and benefits
16-bit bus interface
3-state buffers
Output capability: +64 mA and
32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Power-up 3-state
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Latch-up protection
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVTN16245BDGG
74LVTN16245BBX
40 C
to +85
C
40 C
to +85
C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
SOT1134-1
Type number
HXQFN60U plastic thermal enhanced extremely thin quad
flat package; no leads; 60 terminals; UTLP
based; body 4
6
0.5 mm
NXP Semiconductors
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Fig 1. Logic symbol
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 15 June 2011
2 of 17
NXP Semiconductors
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
1OE
1DIR
G3
3EN1[BA]
3EN2[AB]
2OE
2DIR
G6
6EN4[BA]
6EN5[AB]
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1
2
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
4
5
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aak306
Fig 2. IEC logic symbol
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 15 June 2011
3 of 17
NXP Semiconductors
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVTN16245B
1DIR
1B0
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 V
CC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aak307
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
V
CC
18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
Fig 3.
Pin configuration SOT362-1 (TSSOP48)
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 15 June 2011
4 of 17
NXP Semiconductors
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B13
B15
B16
B17
A25
A24
A23
A22
74LVTN16245B
B14
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aak308
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4.
Pin configuration SOT1134-1 (HXQFN60U)
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 15 June 2011
5 of 17
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