ADC1613S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 2 — 9 June 2011
Product data sheet
1. General description
The ADC1613S is a single channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1613S is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it outputs data in serial mode via a
single differential lane, which complies with the JESD204A standard. The integration of
Serial Peripheral Interface allows the user to easily configure the ADCs and the serial
output modes. The device also includes a programmable full-scale SPI to allow a flexible
input voltage range from 1 V (p-p) to 2 V (p-p).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1613S ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 72.3 dBFS; SFDR, 88 dBc
Sample rates up to 125 Msps
Single channel, 16-bit pipelined ADC
core
3 V, 1.8 V power supplies
Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
Serial output
Power-down mode and Sleep mode
Pin compatible with ADC1413S series,
ADC1213S series, and ADC1113S125
Input bandwidth, 600 MHz
Power dissipation, 550 mW at 80 Msps
SPI register programming
Duty cycle stabilizer
High Intermediate Frequency (IF)
capability
Offset binary, two’s complement, gray
code
Compliant with JESD204A serial
transmission standard
HVQFN32 package
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
NXP Semiconductors
ADC1613S series
Single 16-bit ADC; serial JESD204A interface
4. Ordering information
Table 1.
Ordering information
Sampling
frequency
(Msps)
125
105
80
65
Package
Name
Description
Version
Type number
ADC1613S125HN/C1
ADC1613S105HN/C1
ADC1613S080HN/C1
ADC1613S065HN/C1
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7
7
0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7
7
0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7
7
0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7
7
0.8 mm
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
2 of 39
NXP Semiconductors
ADC1613S series
Single 16-bit ADC; serial JESD204A interface
5. Block diagram
SDIO
SCLK
CS
SPI
SYNCP
SYNCN
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ENCODER 8-bit/10-bit A
FRAME ASSEMBLY
INP
T/H
INPUT
STAGE
INM
ADC CORE
16-BIT
PIPELINED
OTR
D15 to D0
SCRAMBLER A
SERIALIZER A
10-bit
OUTPUT
BUFFER A
CMLP
8-bit
8-bit
CMLN
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
ADC1613S
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
OTR
SENSE
VDDD
AGND
DGND
VDDA
001aam779
Fig 1.
Block diagram
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
3 of 39
NXP Semiconductors
ADC1613S series
Single 16-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
26 SYNCN
25 SYNCP
31 SENSE
28 DGND
30 AGND
27 VDDD
29 VDDA
terminal 1
index area
32 VREF
CLKP
CLKM
AGND
REFB
REFT
VCM
INM
INP
1
2
3
4
24 n.c.
23 DGND
22 DGND
21 VDDD
ADC1613S
5
6
7
8
20 CMLN
19 CMLP
18 VDDD
17 DGND
VDDA 10
SDIO 12
CS 13
OTR 14
VDDD 15
DGND 16
VDDA
SCLK
11
9
001aam781
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2.
Symbol
CLKP
CLKM
AGND
REFB
REFT
VCM
INM
INP
VDDA
VDDA
SCLK
SDIO
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Type
[1]
I
I
G
O
O
O
I
I
P
P
I
I/O
Description
clock input
complementary clock input
analog ground
ADC bottom reference
ADC top reference
ADC output common voltage
ADC complementary analog input
ADC analog input
analog power supply 3 V
analog power supply 3 V
SPI clock
SPI data input/output
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
4 of 39
NXP Semiconductors
ADC1613S series
Single 16-bit ADC; serial JESD204A interface
Pin description
…continued
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Type
[1]
I
O
P
G
G
P
O
O
P
G
G
-
I
I
P
G
P
G
I
I/O
Description
chip select
out-of-range information
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
serial output
serial complementary output
digital power supply 1.8 V
digital ground
digital ground
not connected
positive synchronization signal from the receiver
negative synchronization signal from the receiver
digital power supply 1.8 V
digital ground
analog power supply 3 V
analog ground
reference programming pin
voltage reference input/output
Table 2.
Symbol
CS
OTR
VDDD
DGND
DGND
VDDD
CMLP
CMLN
VDDD
DGND
DGND
n.c.
SYNCP
SYNCN
VDDD
DGND
VDDA
AGND
SENSE
VREF
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DDA
V
DDD(1V8)
T
stg
T
amb
T
j
Parameter
analog supply voltage
digital supply voltage (1.8 V)
storage temperature
ambient temperature
junction temperature
Conditions
Min
0.4
0.4
55
40
-
Max
+4.6
+2.5
+125
+85
125
Unit
V
V
C
C
C
8. Thermal characteristics
Table 4.
Symbol
R
th(j-a)
R
th(j-c)
[1]
Thermal characteristics
Parameter
thermal resistance from junction to ambient
thermal resistance from junction to case
Conditions
[1]
[1]
Typ
25.6
8.6
Unit
K/W
K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
5 of 39
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