PCA9663
Parallel bus to 3 channel Fm+ I
2
C-bus controller
Rev. 1 — 6 June 2011
Product data sheet
1. General description
The PCA9663 is an advanced single master mode I
2
C-bus controller. It is a fourth
generation bus controller designed for data intensive I
2
C-bus data transfers. It has three
independent I
2
C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus
(Fm+) open-drain topology. Each channel has a generous 4352 byte data buffer which
makes the PCA9663 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data.
The PCA9663 is a 8-bit parallel-bus to I
2
C-bus protocol converter. Each channel can be
configured to communicate with up to 64 slaves in one serial sequence with no
intervention from the CPU. The controller also has a sequence loop control feature that
allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I
2
C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external everts. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I
2
C-bus.
Error reporting is handled at the transaction level, channel level and controller level with a
simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller and parallel bus interfaces run at 3.3 V and the I
2
C-bus I/Os are 5 V
tolerant with logic levels referenced to a dedicated V
DD(IO)
input pin with a range of 3.0 V
to 5.5 V.
2. Features and benefits
Parallel-bus to I
2
C-bus protocol converter and interface
1 Mbit/s and up to 30 mA SCL/SDA I
OL
Fast-mode Plus (Fm+) capability
Internal oscillator trimmed to 1 % accuracy reduces external components
Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer
space
Three levels of reset: individual software reset, global software reset, global hardware
RESET pin
Communicates with up to 64 slaves on each channel in one serial sequence
Sequence looping with interval timer
Supports SCL clock stretching
JTAG port available for boundary scan testing during board manufacturing process
Trigger input synchronizes serial communication exactly with external events
NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I
2
C-bus controller
Maskable interrupts
Fast-mode Plus I
2
C-bus capable and compatible with SMBus
Operating supply voltage: 3.0 V to 3.6 V (device and host interface)
I
2
C-bus I/O supply voltage: 3.0 V to 5.5 V
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
ESD protection exceeds 8000 V HBM per JESD22-A114, and 1000 V CDM per
JESD22-C101
Packages offered: LQFP48
3. Applications
Add I
2
C-bus port to controllers/processors that do not have one
Add additional I
2
C-bus ports to controllers/processors that need multiple I
2
C-bus ports
Converts 8 bits of parallel data to serial data stream to prevent having to run a large
number of traces across the entire printed-circuit board
Entertainment systems
LED matrix control
Data intensive I
2
C-bus transfers
4. Ordering information
Table 1.
Ordering information
Topside
mark
PCA9663
Package
Name
LQFP48
Description
plastic low profile quad flat package;
48 leads; body 7
7
1.4 mm
Version
SOT313-2
Type number
PCA9663B
PCA9663
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 June 2011
2 of 66
NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I
2
C-bus controller
5. Block diagram
CE WR RD INT RESET
SDA0
SCL0
Channel 0
Fm+ I
2
C-bus control
STATUS0_[n]
CONTROL
CHSTATUS
INTMSK
SLATABLE
TRANCONFIG
DATA
TRANSEL
TRANOFS
BYTECOUNT
FRAMECNT
REFRATE
SCLL
SCLH
MODE
TIMEOUT
PRESET
Channel 1
Fm+ I
2
C-bus control
STATUS1_[n]
CONTROL
CHSTATUS
INTMSK
SLATABLE
TRANCONFIG
DATA
TRANSEL
TRANOFS
BYTECOUNT
FRAMECNT
REFRATE
SCLL
SCLH
MODE
TIMEOUT
PRESET
Channel 2
Fm+ I
2
C-bus control
STATUS2_[n]
CONTROL
CHSTATUS
INTMSK
SLATABLE
TRANCONFIG
DATA
TRANSEL
TRANOFS
BYTECOUNT
FRAMECNT
REFRATE
SCLL
SCLH
MODE
TIMEOUT
PRESET
PCA9663
TRIG
INTERRUPT
CONTROL
BUFFER
CONTROL
BUS
INTERFACE
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
CTRLSTATUS
CTRLINTMSK
DEVICE_ID
CTRLPRESET
4352-BYTE
BUFFER
CTRLRDY
D5
D6
D7
4352-BYTE
BUFFER
SDA1
SCL1
CONTROL BLOCK
POWER-ON/
POWER-DOWN
RESET
DC/DC
REGULATOR
TCK
TRST
TMS
TDI
TDO
V
DD
SDA2
SCL2
JTAG
4352-BYTE
BUFFER
OSCILLATOR
V
DD(IO)
PLL
002aae940
Fig 1.
PCA9663
Block diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 June 2011
3 of 66
NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I
2
C-bus controller
6. Pinning information
6.1 Pinning
48 V
DD
44 V
DD
43 V
SS
40 V
DD
47 V
SS
39 V
SS
42 D3
41 D2
38 D1
37 D0
36 RESET
35 V
SS
34 TRIG
33 CE
32 RD
31 WR
30 V
DD
29 V
SS
28 SCL0
27 SDA0
26 SCL1
25 SDA1
TRST 13
TMS 14
TCK 15
TDI 16
TDO 17
V
DD
18
V
SS
19
INT 20
SDA2 21
SCL2 22
V
SS(IO)
23
V
DD(IO)
24
002aaf692
46 D5
D6
D7
A0
A1
A2
A3
V
DD
V
SS
A4
1
2
3
4
5
6
7
8
9
45 D4
PCA9663B
A5 10
A6 11
A7 12
Fig 2.
Pin configuration for LQFP48
6.2 Pin description
Table 2.
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
Pin description
Pin
3
4
5
6
9
10
11
12
37
38
41
42
45
46
1
2
Type
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data bus:
bidirectional 3-state data bus used to transfer
commands, data and status between the bus controller and the
host. D0 is the least significant bit. Data is registered on the
rising edge of WR when CE is LOW.
Description
Address inputs:
selects the bus controller’s internal registers
and ports for read/write operations. Address is registered when
CE is LOW and whether WR or RD transitions LOW. A0 is the
least significant bit.
PCA9663
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 June 2011
4 of 66
NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I
2
C-bus controller
Pin description
…continued
Pin
13
14
15
16
17
20
21
22
25
26
27
28
31
Type
I
I
I
I
O
O
O
O
O
O
I/O
I/O
I
Description
JTAG test reset input.
For normal operation, hold LOW (V
SS
).
JTAG test mode select input.
For normal operation, hold HIGH
(V
DD
).
JTAG test clock input.
For normal operation, hold HIGH (V
DD
).
JTAG test data in input.
For normal operation, hold HIGH
(V
DD
).
JTAG test data out output.
For normal operation, do not
connect (n.c.).
Interrupt request:
Active LOW, open-drain, output. This pin
requires a pull-up device.
Channel 2 I
2
C-bus serial data input/output
(open-drain).
This pin requires a pull-up device.
Channel 2 I
2
C-bus serial clock input/output
(open-drain).
This pin requires a pull-up device.
Channel 1 I
2
C-bus serial data input/output
(open-drain).
This pin requires a pull-up device.
Channel 1 I
2
C-bus serial clock input/output
(open-drain).
This pin requires a pull-up device.
Channel 0 I
2
C-bus serial data input/output
(open-drain).
This pin requires a pull-up device.
Channel 0 I
2
C-bus serial clock input/output
(open-drain).
This pin requires a pull-up device.
Write strobe:
When LOW and CE is also LOW, the content of
the data bus is loaded into the addressed register. Data are
latched on the rising edge of WR. CE may remain LOW or
transition with WR.
Read strobe:
When LOW and CE is also LOW, causes the
contents of the addressed register to be presented on the data
bus. The read cycle begins on the falling edge of RD. Data lines
are driven when RD and CE are LOW. CE may transition with
RD.
Chip Enable:
Active LOW input signal. When LOW, data
transfers between the host and the bus controller are enabled
on D0 to D7 as controlled by the WR, RD and A0 to A7 inputs.
When HIGH, places the D0 to D7 lines in the 3-state condition.
During the initialization period, CE must transition with RD until
controller is ready.
Table 2.
Symbol
TRST
TMS
TCK
TDI
TDO
INT
SDA2
SCL2
SDA1
SCL1
SDA0
SCL0
WR
RD
32
I
CE
33
I
TRIG
RESET
34
36
I
I
Trigger input:
provides the trigger to start a new frame.
Reset:
Active LOW input. A LOW level resets the device to the
power-on state. Internally pulled HIGH through weak pull-up
current.
I/O power supply:
3.0 V to 5.5 V. Power supply reference for
I
2
C-bus pins. Sets the voltage reference point for V
IL
/V
IH
.
I/O supply ground.
V
DD(IO)
V
SS(IO)
24
23
power
power
PCA9663
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 June 2011
5 of 66
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