AD9963BCPZ datasheet, PDF - EEWORLD Datasheet

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AD9963BCPZ: DescriptionSPECIALTY ANALOG CIRCUIT, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND4, LFCSP-72; CategoryAnalog mixed-signal IC The signal circuit; File Size3MB，61 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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SPECIALTY ANALOG CIRCUIT, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND4, LFCSP-72

AD9963BCPZ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Rochester Electronics
Parts packaging code	QFN
package instruction	VQCCN,
Contacts	72
Reach Compliance Code	unknown
Analog Integrated Circuits - Other Types	ANALOG CIRCUIT
JESD-30 code	S-XQCC-N72
length	10 mm
Humidity sensitivity level	NOT APPLICABLE
Number of functions	1
Number of terminals	72
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	VQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	1.8 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	NOT SPECIFIED
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	10 mm

AD9963BCPZ Preview

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10-/12-Bit,

Low Power, Broadband MxFE

AD9961/AD9963

FEATURES

Dual 10-bit/12-bit, 100 MSPS ADC

SNR = 67 dB, f

= 30.1 MHz

Dual 10-bit/12-bit, 170 MSPS DAC

ACLR = 74 dBc

5 channels of analog auxiliary input/output

Low power, <425 mW at maximum sample rates

Supports full and half-duplex data interfaces

Small 72-lead LFCSP lead-free package

FUNCTIONAL BLOCK DIAGRAM

AD9961/AD9963

TEMPERATURE

SENSOR

AUX

ADC

DLLFILT

CLKP

CLKN

DLL AND

CLOCK

DISTRIBUTION

AUX

DAC

AUX

DAC

INTERNAL

TXCLK

TXIQ/TXnRX

LPF

1/2/4/8

12-BIT

DAC

TXIP

TXIN

TXQP

TXQN

RXIP

RXIN

MUX

AUXIN1

AUXIO2

AUXIO3

APPLICATIONS

Wireless infrastructure

Picocell, femtocell basestations

Medical instrumentation

Ultrasound AFE

Portable instrumentation

Signal generators, signal analyzers

TXD[11:0]

DATA

ASSEMBLER

TRXCLK

TRXIQ

LPF

1/2

LPF

1/2/4/8

12-BIT

DAC

12-BIT

ADC

GENERAL DESCRIPTION

The AD9961/AD9963 are pin-compatible, 10-/12-bit, low

power MxFE® converters that provide two ADC channels with

sample rates of 100 MSPS and two DAC channels with sample

rates to 170 MSPS. These converters are optimized for transmit

and receive signal paths of communication systems requiring low

power and low cost. The digital interfaces provide flexible

clocking options. The transmit is configurable for 1×, 2×, 4×,

and 8× interpolation. The receive path has a bypassable 2×

decimating low-pass filter.

The AD9961 and AD9963 have five auxiliary analog channels.

Three are inputs to a 12-bit ADC. Two of these inputs can be

configured as outputs by enabling 10-bit DACs. The other

two channels are dedicated outputs from two independent

12-bit DACs.

The high level of integrated functionality, small size, and low

power dissipation of the AD9961/AD9963 make them well-

suited for portable and low power applications.

TRXD[11:0]

LPF

1/2

12-BIT

ADC

RXQP

RXQN

RESET

SDIO

SCLK

REFERENCES

AND BIAS

TXCML

RXCML

REFIO

AUXADCREF

RXBIAS

AUX

DAC

SERIAL

PORT

LOGIC

AUX

DAC

LDO

VREGs

LDO_EN

DAC12A

DAC12B

Figure 1.

PRODUCT HIGHLIGHTS

High Performance with Low Power Consumption.

The DACs operate on a single 1.8 V to 3.3 V supply.

Transmit path power consumption is <100 mW at 170

MSPS. Receive path power consumption is <350 mW at

100 MSPS from 1.8 V supply. Sleep and power-down

modes are provided for low power idle periods.

High Integration.

The dual transmit and dual receive data converters, five

channels of auxiliary data conversion and clock generation

offer complete solutions for many modem designs.

Flexible Digital Interface.

The interface mates seamlessly to most digital baseband

processors.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

08801-001

AD9961/AD9963

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 19

Serial Control Port .......................................................................... 20

General Operation of Serial Control Port ............................... 20

Sub Serial Interface Communications ..................................... 21

Configuration Registers ................................................................. 23

Configuration Register Bit Descriptions ................................. 24

Receive Path..................................................................................... 35

Receive ADC Operation ............................................................ 35

Decimation Filter and Digital Offset ....................................... 36

Transmit Path .................................................................................. 38

Interpolation Filters.................................................................... 38

Transmit DAC Operation.......................................................... 40

Transmit DAC Outputs ............................................................. 42

Device Clocking.............................................................................. 45

Clock Distribution ..................................................................... 45

Driving the Clock Input ............................................................ 46

Clock Multiplication Using the DLL ....................................... 46

Configuring the Clock Doublers .............................................. 47

Digital Interfaces ............................................................................ 48

TRx Port Operation (Full-Duplex Mode) ............................... 48

Single ADC Mode ...................................................................... 48

Tx Port Operation (Full-Duplex Mode) ................................. 49

Half-Duplex Mode ..................................................................... 50

Auxiliary Converters ...................................................................... 52

Auxiliary ADC ............................................................................ 52

Conversion Clock ....................................................................... 52

Auxiliary DACs........................................................................... 53

Power Supplies ................................................................................ 55

Power Supply Configuration Examples ................................... 55

Power Dissipation....................................................................... 55

Outline Dimensions ....................................................................... 58

Ordering Guide .......................................................................... 58

REVISION HISTORY

7/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 60

AD9961/AD9963

SPECIFICATIONS

MIN

to T

MAX

, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, I

OUTFS

= 2 mA, DAC sample rate = 125 MSPS. No

interpolation, unless otherwise noted.

Table 1. Tx Path Specifications

Parameter

TxDAC DC CHARACTERISTICS

Resolution

Differential Nonlinearity

Gain Variation (Internal Reference)

Gain Matching

Offset Error

Full-Scale Output Current (Default Setting)

Output Compliance Range

TXVDD = 3.3 V, V

TXCML

= 0 V

TXVDD = 3.3 V, V

TXCML

= 0.5 V

TXVDD = 1.8 V, V

TXCML

= 0 V

Offset Temperature Drift

Gain Temperature Drift (Internal Reference)

Tx REFERENCE (DEFAULT REGISTER SETTINGS)

Internal Reference Voltage (REFIO)

Output Resistance

Temperature Drift

Adjustment Range (TXVDD = 3 V)

Adjustment Range (TXVDD = 1.8 V)

TxDAC AC CHARACTERISTICS

Maximum Update Rate

Spurious-Free Dynamic Range

OUT

= 5 MHz

OUT

= 20 MHz

Two-Tone Intermodulation Distortion

OUT1

= 5 MHz, f

OUT2

= 6 MHz

OUT1

= 20 MHz, f

OUT2

= 21 MHz

Noise Spectral Density

OUT

= 5 MHz

OUT

= 20 MHz

W-CDMA Adjacent Channel Leakage Ratio, 1 Carrier

DAC

= 122.88 MHz, f

OUT

= 11 MHz

Tx PATH DIGITAL FILTER INPUT RATES

SRRC (8× Interpolation Mode)

INT0 (4× Interpolation Mode)

INT1 (2× Interpolation Mode

Transmit DAC (1× Interpolation Mode)

Min

AD9961

Typ

Max

0.1

0.4

2.0

−0.5

+0.7

−0.5

±40

1.02

±25

0.8

175

−140

−136

21.875

43.75

87.5

175

21.875

43.75

87.5

175

1.2

REFIO

0.8

175

−145

−141

+1.0

+1.7

+0.8

−0.5

+0.7

−0.5

±40

1.02

±25

1.2

REFIO

Min

AD9963

Typ

Max

0.3

0.4

2.0

+1.0

+1.7

+0.8

Unit

Bits

LSB

%FSR

ppm/°C

kΩ

ppm/°C

MSPS

dBc

dBm/Hz

dBc

MHz

−10

−2.4

−0.03

+10

+2.4

+0.03

−10

−2.4

−0.03

+10

+2.4

+0.03

Rev. 0 | Page 3 of 60

AD9961/AD9963

MIN

to T

MAX

, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, ADC sample rate = 100 MSPS. No

decimation, unless otherwise noted.

Table 2. Rx Path Specifications

Parameter

Rx ADC DC CHARACTERISTICS

Resolution

Differential Nonlinearity

Gain Error

Offset Error

Input Voltage Range

Input Capacitance

Rx ADC AC SPECIFICATIONS

Maximum Sample Rate

Spurious Free Dynamic Range

= 10.1 MHz

= 70.1 MHz

Two-Tone Intermodulation Distortion

IN1

= 10 MHz, f

IN2

= 11 MHz

IN1

= 29 MHz, f

IN2

= 32 MHz

Signal-to-Noise Ratio

= 10.1 MHz

= 30.1 MHz

= 70.1 MHz

RXCML OUTPUTS

Output Voltage

Output Current

Rx DIGITAL FILTER CHARACTERISTICS

2× Decimation

Latency (ADC Clock Cycles)

Passband Ripple; f

OUT

DAC

(0.4 × f

DATA

)

Stop-Band Rejection (f

DATA

± 0.4 × f

DATA

)

Min

AD9961

Typ

Max

0.1

±1

±0.5

1.56

100

1.4

0.1

100

1.4

0.1

Min

AD9963

Typ

Max

0.3

±1

±0.5

1.56

Unit

Bits

LSB

%FSR

V p-p diff

MSPS

dBc

dBFS

0.2

Cycles

OUT

DAC

Rev. 0 | Page 4 of 60

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