531AB889M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531AB889M000DG

531AB889M000DG: DescriptionLVPECL Output Clock Oscillator, 889MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531AB889M000DG Overview

LVPECL Output Clock Oscillator, 889MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531AB889M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	889 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Photocell amplification control circuit

Timing control circuit (4)

Multi-purpose home appliance timing controller circuit

A simple indoor humidity controller design

Multifunctional electronic intercom doorbell

555 infrared light controlled "Thank you for coming!" etiquette greeting circuit

Let 8 digital tubes display different numbers at the same time: I'm a beginner Want to know how to make 8 digital tubes display different numbers at the same time My microcontroller does not have a latch. It's best to write a program and see Thanks...; 670357298 51mcu

Baidu found a fun one, share it with you: "Five programmers develop five modules. Each programmer has different efficiency in developing different modules. How to allocate them to ensure the highest efficiency? Please write a program." This i...; yangxf1217 MCU

VirtualAlloc call failed: I'm working on a BSP and debugging. After loading filesys.exe successfully, HeapCreate(0, 0, 0) fails in LMeminit because it returns NULL when calling VirtualAlloc(0x4000000,192512,MEM_RESERVE,PAGE_RE...; liede Embedded System

About djyos: Document link address:http://www.djyos.com/download/Dujiangyan Operating System Introduction - Application Promotion.pdfhttp://www.djyos.com/download/Dujiangyan Operating System Introduction - Kernel ...; djyos Real-time operating system RTOS

Is it normal for the CIII starter board chip to get hot?: This is the CIII starter board for DIY oscilloscopes. The FPGA chip is so hot that you can bake eggs, but it can download normally. I don't know if this is normal? In this case, I dare not use the boa...; lrz123 DIY/Open Source Hardware

MSP-FET430UIF unboxing review PS for identification: I recently developed a project and needed some tools and modules. I was miserable trying to find them. I was also very uncertain, so I placed an order from one of the Taobao stores just for fun. The m...; 海得工控 Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components