datasheet
EEWORLDEEWORLDEEWORLD
Datasheet
Part Number

Keyword

Search
Keyword

Part Number

Search
Datasheet> All Categories > Discrete semiconductor> The transistor> FSYC163D3
PDF
Preview

FSYC163D3

Description
Power Field-Effect Transistor, 62A I(D), 130V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN
CategoryDiscrete semiconductor    The transistor   
File Size110KB，8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

FSYC163D3 Overview

Power Field-Effect Transistor, 62A I(D), 130V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN

FSYC163D3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
package instructionSMD2, 3 PIN
Contacts3
Reach Compliance Codecompliant
ECCN codeEAR99
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage130 V
Maximum drain current (Abs) (ID)62 A
Maximum drain current (ID)62 A
Maximum drain-source on-resistance0.03 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-CBCC-N3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)83 W
Maximum pulsed drain current (IDM)186 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON

FSYC163D3 Preview

FSYC163D, FSYC163R
Data Sheet
December 2001
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFETs
The Discrete Products Operation of Fairchild has developed
a series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity to Single Event Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with 100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space
environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.
The Fairchild portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Fairchild for any desired deviations
from the data sheet.
Features
• 62A, 130V, r
DS(ON)
= 0.030
Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 12.5nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Symbol
D
G
S
Packaging
SMD2
Ordering Information
RAD LEVEL
10K
10K
100K
100K
100K
SCREENING LEVEL
Commercial
TXV
Commercial
TXV
Space
PART NUMBER/BRAND
FSYC163D1
FSYC163D3
FSYC163R1
FSYC163R3
FSYC163R4
Formerly available as type TA45203.
©2001 Fairchild Semiconductor Corporation
FSYC163D, FSYC163R Rev. B
Absolute Maximum Ratings
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20k
Ω
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Derated Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
FSYC163D, FSYC163R
130
130
62
39
186
±
20
208
83
1.67
186
62
186
-55 to 150
300
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
130
-
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 12V
V
GS
= 0V to 2V
V
DD
= 65V,
I
D
= 62A
-
-
-
-
-
I
D
= 62A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.022
-
-
-
-
-
-
170
-
28
94
8
4300
1300
500
-
MAX
-
5.0
4.0
-
25
250
100
200
1.95
0.030
0.049
50
210
100
45
300
200
8.2
34
120
-
-
-
-
0.6
UNITS
V
V
V
V
µ
A
µ
A
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(12)
Q
g(TH)
Q
gs
Q
gd
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= 104V,
V
GS
= 0V
V
GS
=
±
20V
V
GS
= 12V, I
D
= 62A
I
D
= 39A,
V
GS
= 12V
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge at 12V
Threshold Gate Charge
Gate Charge Source
Gate Charge Drain
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
V
DD
= 65V, I
D
= 62A,
R
L
= 1.0
Ω
, V
GS
= 12V,
R
GS
= 2.35
Ω
©2001 Fairchild Semiconductor Corporation
FSYC163D, FSYC163R Rev. B
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
I
SD
= 62A
I
SD
= 62A, dI
SD
/dt = 100A/
µ
s
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 104V
V
GS
= 12V, I
D
= 62A
V
GS
= 12V, I
D
= 39A
MIN
130
1.5
-
-
-
-
MAX
-
4.0
100
25
1.95
0.030
UNITS
V
V
nA
µA
V
Ω
TEST CONDITIONS
MIN
0.6
-
TYP
-
-
MAX
1.8
670
UNITS
V
ns
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
ION
SPECIES
Ni
Br
Br
Br
Br
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm
2
(typical), T = 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
26
37
37
37
37
TYPICAL
RANGE (µ)
43
36
36
36
36
APPLIED
V
GS
BIAS
(V)
-20
-5
-10
-15
-20
(NOTE 6)
MAXIMUM
V
DS
BIAS (V)
130
130
104
78
52
Typical Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm
2
, RANGE = 43µ
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LIMITING INDUCTANCE (HENRY)
140
120
100
V
DS
(V)
80
60
40
20
0
0
TEMP = 25
o
C
-5
-10
-15
V
GS
(V)
-20
-25
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
1E-3
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
©2001 Fairchild Semiconductor Corporation
FSYC163D, FSYC163R Rev. B
Typical Performance Curves
80
Unless Otherwise Specified
(Continued)
500
T
C
= 25
o
C
60
I
D
, DRAIN CURRENT (A)
100
I
D
, DRAIN (A)
100µs
40
10
20
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1ms
10ms
0
-50
0
50
100
150
1
1
10
100
300
T
C
, CASE TEMPERATURE (
o
C)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 39A
2.0
NORMALIZED r
DS(ON)
12V
Q
G
1.5
Q
GS
V
G
Q
GD
1.0
0.5
CHARGE
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
10
THERMAL RESPONSE (Z
θJC
)
1
0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
+ T
C
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
t
1
t
2
10
0
10
1
NORMALIZED
0.1
P
DM
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
©2001 Fairchild Semiconductor Corporation
FSYC163D, FSYC163R Rev. B
Typical Performance Curves
1000
I
AS
, AVALANCHE CURRENT (A)
Unless Otherwise Specified
(Continued)
100
STARTING T
J
= 150
o
C
10
STARTING T
J
= 25
o
C
1
0.01
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
V
DD
t
ON
t
d(ON)
t
OFF
t
d(OFF)
t
r
t
f
90%
R
L
V
DS
V
GS
= 12V
DUT
0V
R
GS
V
DS
90%
10%
10%
90%
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSYC163D, FSYC163R Rev. B
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

FSYC163D3 Related Products

FSYC163D3
Description Power Field-Effect Transistor, 62A I(D), 130V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN
Is it Rohs certified? incompatible
Maker Fairchild
package instruction SMD2, 3 PIN
Contacts 3
Reach Compliance Code compliant
ECCN code EAR99
Shell connection DRAIN
Configuration SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 130 V
Maximum drain current (Abs) (ID) 62 A
Maximum drain current (ID) 62 A
Maximum drain-source on-resistance 0.03 Ω
FET technology METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-CBCC-N3
JESD-609 code e0
Number of components 1
Number of terminals 3
Operating mode ENHANCEMENT MODE
Maximum operating temperature 150 °C
Package body material CERAMIC, METAL-SEALED COFIRED
Package shape RECTANGULAR
Package form CHIP CARRIER
Peak Reflow Temperature (Celsius) NOT SPECIFIED
Polarity/channel type N-CHANNEL
Maximum power dissipation(Abs) 83 W
Maximum pulsed drain current (IDM) 186 A
Certification status Not Qualified
surface mount YES
Terminal surface Tin/Lead (Sn/Pb)
Terminal form NO LEAD
Terminal location BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED
transistor applications SWITCHING
Transistor component materials SILICON

Recommended Resources

One of the forward and reverse circuits of DC motor armature connected with resistor in series to start reverse braking

Electric mixer intermittent operation controller circuit

LM2575-5.0 step-down switching regulator basic application circuit diagram

Humidity monitor

50w ISNE541 high-fidelity amplifier circuit

Undervoltage dedicated integrated chip MC3X164 series internal circuit block diagram

The tool is still in Beta state
A: This tool is still in Beta state. This happens every time I start As shown in the figure: B: Delete the ssh configuration and try again. It will be regenerated....
明远智睿Lan Industrial Control Electronics
No explanation, please.
Download (30.55 KB) 2009-9-16 16:53Download (32.04 KB) 2009-9-16 16:53...
smnh1 stm32/stm8
Why are garbled characters displayed when using 12864 LCD graphics mode?
The basic command can display characters or Chinese characters normally, but when the extended command's graphic mode is used, garbled characters appear on the screen, although the characters are stil...
zhulide Embedded System
keil
bit Ircv(uchar sla, uchar *s) { Start_I2c();/*Start bus*/ SendByte(sla); /*Send device address*/ if(ack==0)return(0); *s=RcvByte(); /*Send data*/ Ack_I2c(1); /*Send non-response bit*/ Stop_I2c(); /*En...
langlangzhi Embedded System
How is MMS processed under wince
Can any expert answer this for me, thanks....
liu9952585 Embedded System
Registration for TI's Battery Management Seminar Series is now open!
This summer, Texas Instruments (TI) will hold a series of battery management seminars in Beijing, China, and Taiwan. sans-serif]Shanghai, Shenzhen, Dongguan, and Shenzhen have launched the new product...
EEWORLD社区 Analogue and Mixed Signal
Shortcut:   E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components

  1. 222K174-100/180-0
  2. EQDP-014-21.59-TTL-SED-1
  3. CRA12E16297R6FTR
  4. XSCB2251560AB
  5. SV13KA361MAATR1
  6. LOT67F
  7. SIP-4788SD-02-4641FA
  8. VM14E5-14.400-3/0+60
  9. A2541WR-2x8P-E229-G30
  10. CR2512J110RE04Z
  11. QR0603D3K44P05
  12. SLR0364DWC1BD

Popular Articles

  1. Circuit breaker mechanical characteristics tester operation steps
  2. HUAYU Automotive 4D Imaging Millimeter Wave Radar R&D Completes Four Seasons of Mass Production
  3. 51 Single Chip Microcomputer-Practical Operation
  4. SMIC invests 57.3 billion to build 12-inch wafer fab in Shanghai
  5. Rockwell Automation Introduces New CENTERLINE 1500 Motor Control Center Grounding Device
  6. LANXESS develops new automotive radar sensor concept with integrated thermal management
  7. Great Wall Dayu Battery reveals the technological breakthrough that turns congestion into traffic flow: making all electric vehicles fire-proof and explosion-proof
  8. K-type thermocouple program Proteus test based on ATMEGA8A microcontroller + MAX6675
  9. Taxi meter project design
  10. Surpass Yourself, Pursue Global Dreams | RT-Thread Developer Conference Concludes Successfully!

Technical ResourceMore

  1. A collection of new practical power amplifier circuits
  2. FM3817 Bluetooth module information
  3. C language learning system version 3.2
  4. NSJS16R1 Learning Board Quick Learning Guide
  5. Driving the ADC14DS105 high-speed analog/digital converter for high performance
  6. Design of Display Driver for Handheld Digital Storage Oscilloscope Based on FPGA
  7. NSW1824C router upgrade package
  8. Principle and Application of Eight-Channel 13-Bit Digital-to-Analog Converter MAX547
  9. Smart car microcontroller program and report + flow chart + pin description
  10. Capture to Allegro Interface

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews
Index Files: 2395  1604  2697  2521  1483  49  33  55  51  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号