Common Bus CPU Card (C3)
Family for 64-bit MIPS
Processors
FEATURES:
• Supports IDT Common Bus CPU Card (C3) electrical and
mechanical specifications.
• C3 Card family supports IDT 64bit MIPS family including R4650,
R4700, R64475, R5000, R64575 for easy scaling of performance.
• Low profile, mezzanine form-factor. Ideal daughtercard for:
– Compact PCI
– VME
– Ethernet / ATM switches
• Utilizes SAMTEC CLP connectors
– 100 pin Conn. A: part number: CLP-150-02-L-D-PA
– 96 pin Conn. B: part number: CLP-148-02-L-D-PA
• Onboard clock generation circuitry for processor/system
clocks
• Onboard processor reset and configuration circuitry.
• 5V Tolerance
PRELIMINARY
IDT7M9516 IDT7M9521
IDT7M9518 IDT7M9522
IDT7M9519 IDT7M9523
IDT7M9520
DESCRIPTION:
The C3 family are CPU mezzanine daughtercards based on IDT's MIPS
processors. The C3 Card family is designed to replace the CPU and specific
support circuitry around the CPU in a system design. The goal of the C3 is
to provide the system designer a seamless hardware migration path
through IDT's family of 64-bit MIPS processors(R4650, R4700, R64475,
R5000, R64575), and to simplify the overall system implementation require-
ments of those processors.
Each of the above processors has a unique pin configuration/package;
therefore, a system designer would normally be required to implement a
unique board design for each of the processors. The goal of the C3 is to
eliminate the differences between these processors at the system interface
level, and to allow the system designer to implement a single baseboard
design which will support C3 cards featuring the R4650, R4700, R64475,
R5000, R64575 or future processors.
FUNCTIONAL BLOCK DIAGRAM
Reset
Generation
MIPS CPU
Configuration
Logic
SysAD , etc.
CLO CK
GEN ERATION
SyncO ut
SyncIn
C3/System
Boundary
System
Clocks
SyncOut m ust be tied to
SyncIn for proper operation
Configuration
Inputs
4266 dwg 01
JULY 1999
1
©
1999
Integrated Device Technology, Inc.
DSC-4266/2
IDT7M9516/18/19/20/21/22/23
IDT
BOARD OVERVIEW
The C3 processor cards consist of the following functional blocks: 64bit
MIPS CPU, clock generation circuitry for the processor/system clocks,
processor reset and configuration circuitry, and an optional L2 cache
subsystem.
CLOCK GENERATION
The C3 provides nine clock outputs that are associated with system bus clock
generation, as well as a 20MHz clock output and a 24MHz clock output. The
ten bus clock outputs consist of nine identical buffered system clocks and one
dedicated output for processor to system clock synchronization. The system
clocks - SysCLK(0:8) - are provided to drive devices on the system bus, as well
as other devices that need to operate at the system clock frequency. The
processor synchronization clock output (SyncOut) must be connected to the
processor synchronization clock input (SyncIn) through a delay path that
matches the delay path of the system clocks to ensure proper operation of the
C3 in the system. The 20MHz and 24MHz clocks are provided for system
peripherals that have fixed frequency requirements.
RESET CONFIGURATION
The C3 contains on board reset generation logic that provides all of the
reset requirements of the processor. This reset logic handles all Power On
Reset requirements, as well as handling two system hard reset sources
(S_HardRST*, A_HardRST*) and a system soft reset source (SoftRST*).
In addition, the reset logic of the C3 also provides a reset output (RSTOut*)
to the system that is asserted whenever there is a processor hard reset.
WATCHDOG TIMER
The watchdog timer input (WDStrb pin B-172) of the C3 must be strobed
periodically to prevent the watchdog timer output (WDO* pin B-173) from being
asserted. If the input is not strobed within 1 second of the previous strobe, the
output will be asserted. Note that if the watchdog timer functionality is not required,
these pins can be left unconnected.
C3 CONFIGURATION
The C3 is configured through a set of static configuration inputs. The
configuration inputs are used for both C3 clock configuration and proces-
sor configuration. The clock configuration inputs are used to set the
system bus clock frequency and the CPU core to system bus clock
multiplier. The processor configuration inputs are used to configure the
following: endianess (big/little), drive strength (83%/100%), internal timer
(enabled/disabled), write type (R4X00/pipelined) and block write data rate
(D/Dx/Dxx/Dxxx).
5V TOLERANCE CIRCUITRY
5V tolerance is provided by running the signals through bus switches.
All inputs and I/O's are 5V tolerant except for SYNCIN. The input voltage
on SYNCIN must not exceed VCC3 + 0.3V. (Not available on 7M9521 and
7M9522).
PACKAGE DIMENSIONS
TOP VIEW
BOTTOM VIEW
.0 5 0
2 .0 1 3
.0 50
P in 1
.169 R E F
.0 5 0 T Y P
P in 1
0.50
P in 1 4 9
FST
PAL
FST
C L K GE N
XTA L
FS T
. 07 5 R E F
FST
2.60
FST
FST
FST
FS T
FS T
CLK D RV
M IP S
CPU
2 .6 0 0
(+ / - 0 .0 1 0 )
FST
2.45
P in 1 9 6
4266 dwg 2A
NOTES:
1. All dimensions in inches.
2. Actual component placement may differ from those shown in the diagram.
2 .4 5 0
(+ / - 0 . 0 1 0 )
P in 5 0
4266 dwg 05
2
©
1999
Integrated Device Technology, Inc.
DSC-4266/2
IDT7M9516/18/19/20/21/22/23
IDT
C onnector B
V CC 5
SysC M D (7)
GND
SysAD( 9)
SysAD (4 0)
SysC M D (5)
ScTC E*
A _Hard Rst*
C lkM ult(2)
SysADC (0)
SysAD (3 9)
GND
RSVD
SysC M D (3)
SysAD( 6)
V CC 3
SysAD (3 7)
SysC M D (2)
SysAD( 4)
GND
SysAD (3 5)
SysC M D (0)
SysAD( 2)
V CC 3
IN T4*
SysAD( 1)
SysAD (3 2)
V CC 3
IN T3*
SysAD (1 6)
IN T1*
V CC 3
SysAD (4 9)
SysAD (1 8)
ValidIn*
GND
RSVD
SysAD (5 1)
SysAD (5 2)
V CC 3
ValidO ut*
RSVD
GND
SysAD (5 3)
SysAD (2 2)
SysAD (5 5)
V CC 3
SysAD P(2)
SysAD P(6)
V CC 5
PINOUT
(1)
VCC 5
SysAD (10)
SysAD (41)
SysC M D (6)
GND
Sys AD(8)
C lkM ult(0)
C lkM ult(1)
GND
SysAD P(4)
RSVD
SysC M D (4)
GND
Sys AD(7)
SysAD (38)
W rR dy*
GND
Sys AD(5)
SysAD (36)
GND
SysC M D (1)
Sys AD(3)
GND
SysAD (34)
IN T5*
SysAD (33)
GND
Sys AD(0)
IN T2*
GND
SysAD (48)
SysAD (17)
GND
IN T0*
SysAD (50)
GND
SysAD (19)
SysAD (20)
GND
SysAD (21)
RELEASE*
GND
R dR dy*
SysAD (54)
GND
SysAD (23)
N MI*
GND
SysAD (24)
VCC 5
C onnector A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC5
S _ H a rd R s t*
O u tD rv
S o ftR s t*
GND
20M H zOut
GND
24 M h zO u t
GND
S ysA D (4 2)
S ysA D (1 1)
S ysA D (1 2)
VCC3
S ysA D (1 3)
B lk W r( 0 )
B lk W r( 1 )
VCC3
S ysA D (1 4)
S ysA D (1 5)
S y s A D P (1 )
GND
S y s C lk (8 )
E n d ia n
VCC3
S y n c In
VCC3
S y s C lk (1 )
VCC3
S yn cO u t
VCC3
S ysC L K (3)
VCC3
S ysC L K (5)
VCC3
S ysC L K (7)
VCC3
S y s A D P (7 )
GND
S ysA D (6 3)
S ysA D (6 2)
S ysA D (2 9)
VCC3
S ysA D (2 8)
S ysA D (2 7)
S ysA D (2 6)
GND
S ysA D (5 6)
VCC5
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
1 2 2
(2)
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
VCC5
C L K F re q (0 )
C L K F re q (1 )
C L K F re q (2 )
ScDO E*
GND
S c W o rd (0 )
S c W o rd (1 )
L 2 _ H it
SysC M D (8)
GND
S y s A D (4 3 )
S y s A D (4 4 )
S y s A D (4 5 )
GND
T im e r E n *
W rType
RSVD
GND
S y s A D (4 6 )
S y s A D (4 7 )
S y s A D P (5 )
GND
W D _ S tr b
WDO*
R s tO u t*
GND
S y s C L K (0 )
GND
S y s C L K (2 )
GND
S y s C L K (4 )
GND
S y s C L K (6 )
GND
E x tR e q *
S y s A D C (3 )
S y s A D (3 1 )
S y s A D (3 0 )
GND
S y s A D (6 1 )
S y s A D (6 0 )
S y s A D (5 9 )
GND
S y s A D (5 8 )
S y s A D (5 7 )
S y s A D (2 5 )
VCC5
NOTE:
1. The pinout of the C3 card is from a top view.
2. This pin is not connected (NC) on the 7M9516.
4266 dwg 03
3
©
1999
Integrated Device Technology, Inc.
DSC-4266/2
IDT7M9516/18/19/20/21/22/23
IDT
PIN DEFINITIONS
Signal Name
SysAD(63:0)
Signal Definition
System (CPU)
Address/Data Bus
Type
I/O
Description
64-bit multiplexed address/data bus. This bus is driven by the C3 during the address
phase (SysCMD(8)=0) of a bus transaction. Valid data is driven by the C3 during the
data phase (SysCMD(8)=1) for writes when ValidOut* is asserted. The C3 receives
data on this bus during the data phase for reads when ValidIn* is sampled low.
Even parity is generated during the data phase for writes. Even parity is checked during
the data phase for reads if SysCMD(4) is low. Timing and valid sample windows match
SysAD(63:0). SysADP(0) is assosciated with SysAD(7:0), SysADP(1) is associated
withSysAD(15:8).
This is the 9-bit processor command bus.
Nine identical clocks for devices residing on the C3 processor bus. All processor
transitions/transactions are referenced with respect to these clocks.
The C3 system clock generator synchronization output must be connected to SyncIn
through an interconnect scheme that matches that used on SysCLK(8:0).
C3 system clock generator synchronization input. This pin must be connected to
SyncOut for the C3 to operate.
This pin is driven low by the system to indicate that the system is ready to accept a C3 read
request.
This pin is driven low by the system to indicate that the system is ready to accept a C3
write request.
This pin is driven low by the C3 to indicate that it is driving a valid address/data on the SysAD,
SysADP and SysCMD busses.
This pin in driven low by the system to indicate that it is presenting valid address/data on
the SysAD, SysADP and SysCMD busses.
Endian configuration input.
0=big, 1=little
Output drive strength configuration input.
0=100%, 1=83%
CPU internal timer interrupt enable configuration input.
0=enable timer, 1=disable timer
Write Type configuration input.
0=R4X00 compatible, 1=Pipelined
000=x2
001=x3
010=x4
011=x5
100-101=reserved
110=SmartClock mode 0 (max CPU core frequency)
111=SmartClock mode 1(max CPU bus frequency)
Block Write data rate
00=DDDD
01=DxDxDxD
10=DxxDxxDxxD
11=DxxxDxxxDxxxD
This pin is driven low to signal to the requesting device that the system interface is available.
SysADP(7:0)
SysAD Parity
I/O
SysCMD(8:0)
SysCLK(8:0)
SyncOut
SyncIn
Clock Input
RdRdy*
WrRdy*
ValidOut*
ValidIn*
Endian
OutDrv
TimerEn*
WrType
ClockMult(2:0)
System (CPU)
command/data
System (CPU)
Clocks
Synchronization
Clock Output
Synchronization
Read Ready
Write Ready
Valid Output
Valid Input
Endian
Output Drive
Timer Enable
Write Type
Clock Multiplier
I/O
Output
Output
Input
Input
Input
Output
Input
Config
Input
Config
Input
Config
Input
Config
Input
Config
Input
BlkWr(1:0)
Block Write
Config
Input
RELEASE*
Release Interface
Output
ExtReq*
External Request
Intput
This pin is driven low to request the use of the system interface.
4266 tbl 01
4
©
1999
Integrated Device Technology, Inc.
DSC-4266/2
IDT7M9516/18/19/20/21/22/23
IDT
PIN DEFINITIONS (CONTINUED)
Signal Name
ClkFreq(2:0)
Signal Definition
SysCLK
Frequency
Type
Config
Input
Description
In normal mode these inputs specify the system bus clock frequency. In SmartClock
mode, these inputs specify the maximum system clock frequency.
000=45MHz (includes 43.75/44)
100=75MHz
001=50MHz
101=83MHz
010=60MHz (includes 58.33)
110=90MHz
011=66MHz
111=100MHz
General processor interrupts.
Non-maskable interrupt
Asserting this input causes a processor soft (or warm) reset.
Asserting this input causes a processor hard (or cold) reset.
Asserting this input causes a processor hard (or cold) reset.
This pin is asserted by the C3 to reset system logic. This output is asserted during
power-on reset, and whenever HardRST* is asserted.
This pin asserted by the C3 whenever there is a timeout of the watchdog
timer.
This pin must be strobed periodically by the system to prevent the Strobe watchdog timer
from timing out.
This pin indicates to the system that a hit has occurred in the on board
L2 cache. This pin is a no connect on the 7M9516/18/19/20/23.
Only used when a secondary cache is implemented with the R5K internal
cache controller. This pin is a no connect on the 7M9516/18/19/20/23.
Only used when a secondary cache is implemented with the R5K internal
cache controller
This pin indicates to the system when the L2 cache controller of the R5K is accessing the
Tag RAM. This pin is driven high by the 7M9516/18/19/20/23.
20MHz Clock
24MHz Clock
System Ground
System 3.3V Supply
System 5V Supply
4266 tbl 03
INT*(5:0)
NMI*
SoftRST*
S_HardRST*
Hard Reset
A_HardRST*
Hard Reset
RSTOut*
WDO*
WD_Strb
L2_HIT
(ScMatch)
ScDOE*
Interrupts
Non-Maskable
Interrupt
Soft Reset
Synchronous
Asynchronous
Reset Output
Watch Dog
Output
Watch Dog
L2 Cache Hit
Secondary
Cache Data
OE*
Secondary
Cache Word
Secondary Cache
Tag Chip Enable
20MHz Clock
24MHz Clock
Ground
+3.3V
+5V
Input
Input
Input
Input
Input
Output
Output
Input
Output
Input
ScWord(1:0)
ScTCE*
20MHz Out
24MHz Out
GND
VCC3
VCC5
I/O
Output
Output
Output
Supply
Supply
Supply
ENVIRONMENTAL
Operating
Non-Op.
Storage
NOTE:
1. Non-Condensing
Temp. (°C)
Min
Max
0
55
-10
60
-25
60
Humidity
(1)
Condition
Min
Max
20%
80%
10%
90%
10%
90%
4266 tbl 02
5
©
1999
Integrated Device Technology, Inc.
DSC-4266/2
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