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HY27SS08561A-SPCB

Description
Flash, 32MX8, 35ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, USOP1-48
Categorystorage    storage   
File Size423KB,47 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance  
Download Datasheet Parametric View All

HY27SS08561A-SPCB Overview

Flash, 32MX8, 35ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, USOP1-48

HY27SS08561A-SPCB Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeSOIC
package instructionVSSOP, TSSOP48,.71,20
Contacts48
Reach Compliance Codecompliant
ECCN code3A991.B.1.A
Maximum access time35 ns
command user interfaceYES
Data pollingNO
JESD-30 codeR-PDSO-G48
length15.4 mm
memory density268435456 bit
Memory IC TypeFLASH
memory width8
Number of functions1
Number of departments/size2K
Number of terminals48
word count33554432 words
character code32000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX8
Package body materialPLASTIC/EPOXY
encapsulated codeVSSOP
Encapsulate equivalent codeTSSOP48,.71,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
page size512 words
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Programming voltage1.8 V
Certification statusNot Qualified
ready/busyYES
Maximum seat height0.65 mm
Department size16K
Maximum standby current0.00005 A
Maximum slew rate0.015 mA
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
switch bitNO
typeSLC NAND TYPE
width12 mm
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Document Title
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Change AC Parameter
tCRY(1.8V)
Before
50+tr(R/B#)
60+tr(R/B#)
History
Draft Date
Apr. 04. 2005
Remark
Preliminary
0.1
After
Jul. 07. 2005
Preliminary
2) Change 256Mb Package Type.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
1)
Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
CC1)
Before
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
t
RC
=50ns,
CE#=
V
IL
,
I
OUT
=0mA
t
RC
(1.8V=60ns,
3.3V=50ns)
CE#=
V
IL
,
I
OUT
=0mA
After
VIN=VOUT=0 to Vcc (max)
0.2
2)
Change AC Conditions table
3)
Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit Copy Back Program operation step
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
7) Change NOP (table 11)
Main Array
Before
After
1
2
Aug. 08. 2005
Preliminary
Spare Array
2
3
Rev 0.5 / Jun. 2006
1
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