MT46V256M4P-75 datasheet, PDF - EEWORLD Datasheet

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MT46V256M4P-75: DescriptionDDR DRAM, 256MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSOP-66; Categorystorage storage; File Size3MB，82 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46V256M4P-75 Overview

DDR DRAM, 256MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSOP-66

MT46V256M4P-75 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	TSOP
package instruction	TSSOP, TSSOP66,.46
Contacts	66
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e3
length	22.22 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	66
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.01 A
Maximum slew rate	0.485 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	10.16 mm

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1Gb: x4, x8, x16 DDR SDRAM

Features

DDR SDRAM

MT46V256M4 – 64 Meg x 4 x 4 Banks

MT46V128M8 – 32 Meg x 8 x 4 Banks

MT46V64M16 – 16 Meg x 16 x 4 Banks

Features

• V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

= +2.6V ±0.1V, V

Q = +2.6V ±0.1V (DDR400)

• Bidirectional data strobe (DQS) transmitted/

received with data, that is, source-synchronous data

capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

(x16 has two – one per byte)

• Programmable burst lengths (BL): 2, 4, or 8

• Auto refresh and self refresh modes

• Longer-lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

• Concurrent auto precharge option is supported

•

RAS lockout supported (

RAP =

RCD)

Options

• Configuration

–

256 Meg x 4 (64 Meg x 4 x 4 banks)

–

128 Meg x 8 (32 Meg x 8 x 4 banks)

–

64 Meg x 16 (16 Meg x 16 x 4 banks)

• Plastic package – OCPL

–

66-pin TSOP

(400-mil width, 0.65mm pin pitch)

–

66-pin TSOP (Pb-free)

(400-mil width, 0.65mm pin pitch)

• Timing – cycle time

–

5.0ns @ CL = 3 (DDR400B)

–

6.0ns @ CL = 2.5 (DDR333B)

–

7.5ns @ CL = 2.5 (DDR266B)

• Temperature rating

–

Commercial (0°C to +70°C)

–

Industrial (–40°C to +85°C)

• Revision

Marking

256M4

128M8

64M16

-5B

-6T

-75

None

Notes: 1. Not recommended for new designs.

2. See Table 3 on page 2 for module

compatibility.

Table 1:

Key Timing Parameters

CL = CAS (READ) latency; data-out window is MIN clock rate with 50 percent duty cycle at CL = 2.5

Clock Rate (MHz)

Data-Out

Window

1.6ns

2.0ns

2.5ns

Access

Window

±0.70ns

±0.75ns

DQS–DQ

Skew

+0.40ns

+0.45ns

+0.50ns

Speed Grade

-5B

-6T

-75

CL = 2

133

100

CL = 2.5

167

133

CL = 3

200

n/a

PDF: 09005aef80a2f898/Source: 09005aef82a95a3a

1Gb_DDR_x4x8x16_D1.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb: x4, x8, x16 DDR SDRAM

Table of Contents

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical Specifications – I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

PDF: 09005aef80a2f898/Source: 09005aef82a95a3a

1Gb_DDRTOC.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb: x4, x8, x16 DDR SDRAM

Functional Description

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n-prefetch architecture with an inter-

face designed to transfer two data words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-

cycle data transfer at the internal DRAM core and two corresponding

n-bit-wide,

one-

half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in

data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during

READs and by the memory controller during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,

one for the lower byte and one for the upper byte.

The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which may then

be followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVE command are used to select the bank and row to be accessed. The address

bits registered coincident with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8

locations. An auto precharge function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs

allows for concurrent operation, thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All

inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs

are SSTL_2, Class II compatible.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated

otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper

byte. For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For

the upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.

• Complete functionality is described throughout the document and any page or

diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

PDF: 09005aef80a2f898/Source: 09005aef82a95a3a

DDR_x4x8x16_Core1.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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