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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 843003AGI-01T
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843003AGI-01T

Description
Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB，16 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

843003AGI-01T Overview

Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24

843003AGI-01T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts24
Reach Compliance Codenot_compliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length7.8 mm
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency680 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Master clock/crystal nominal frequency27.2 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate150 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

843003AGI-01T Preview

FEMTOCLOCK™ CRYSTAL-TO-3.3V
LVPECL FREQUENCY SYNTHESIZER
ICS843003I-01
G
ENERAL
D
ESCRIPTION
The ICS843003I-01 is a 3 differential output
LVPECL Synthesizer designed to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member of
the HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequencies
can be generated based on the settings of 4 frequency select
pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz. The 843003I-01 has 2 output banks,
Bank A with 1 differential LVPECL output pair and Bank B with
2 differential LVPECL output pairs.
F
EATURES
• Three 3.3V LVPECL outputs on two banks, A Bank with one
LVPECL pair and B Bank with two LVPECL output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.53ps (typical)
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
IC
S
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies
m e n t i o n e d a b ove. T h e I C S 8 4 3 0 0 3 I - 0 1 u s e s I C S ’ 3 r d
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Ether net jitter requirements. The ICS843003I-01 is
packaged in a small 24-pin TSSOP package.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
CCO
_
A
QA0
nQA0
OEB
OEA
QA0
FB_DIV
nQA0
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
CCO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
V
EE
DIV_SELA1
OEA
Pullup
DIV_SELA[1:0]
Pullup
VCO_SEL
Pullup
REF_CLK
Pulldown
0
0
00
01
10
11
÷1
÷2
÷3
÷4
(default)
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
ICS843003I-01
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷2
÷4
÷5
÷8
(default)
nQB0
QB1
nQB1
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
FB_DIV
Pulldown
DIV_SELB[1:0]
Pullup
MR
Pulldown
OEB
Pullup
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843003AGI-01 REV A March 2, 2009
ICS843003I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
24
2
Name
DIV_SELB0
DIV_SELB1
VCO_SEL
Type
Input
Description
Division select pin for Bank B. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed by
default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the 2
output pairs on Bank B are enabled. When logic LOW, the output pairs drive
differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so
the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the
output pair on Bank A is enabled. When logic LOW, the output pair drives
differential Low (QA0=Low, nQA0=High). Has an internal pullup resistor so
the default power-up state of outputs are enabled. LVCMOS/LVTTL interface
levels.
Feedback divide select. When Low (default), the feedback divider is set for
÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Input
3
MR
Input
4
5, 6
V
CCO_A
QA0, nQA0
Power
Ouput
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15, 16
FB_DIV
V
CCA
V
CC
DIV_SELA0
DIV_SELA1
V
EE
XTAL_OUT,
XTAL_IN
REF_CLK
Input
Power
Power
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
XTAL_SEL
nQB1, QB1
nQB0, QB0
Input
Output
Output
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to pull
Pulldown to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
Pullup
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Power
Output supply pin for Bank B outputs.
23
V
CCO_B
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843003AGI-01 REV A March 2, 2009
ICS843003I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DIV_SELA1 DIV_SELA0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
32
32
32
32
32
32
32
Bank A
Output Divider
1
2
2
3
4
4
4
1
2
2
3
4
4
4
M/N
Multiplication
Factor
25
12.5
12.500
8.333
6.25
6.25
6.25
32
16
16
10.667
8
8
8
QA0/nQA0
Output
Frequency
(MHz)
625
312.5
250
187.5
156.25
150
125
622.08
311.04
250
200
155.52
150
125
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
20
25
24
20
25
25
24
20
19.44
15.625
19.44
18.75
15.625
15.625
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DIV_SELB1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
DIV_SELB0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
Bank B
Output Divider
2
2
4
4
4
5
8
8
8
2
2
4
4
4
5
8
8
8
M/N
Multiplication
Factor
12.5
12.5
6.25
6.25
6.25
5
3.125
3.125
3.125
16
16
8
8
8
6.4
4
4
4
QBx/nQBx
Output
Frequency
(MHz)
312.5
250
156.25
150
12 5
125
78.125
75
62.5
311.04
250
155.52
150
125
10 0
77.76
75
62.5
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843003AGI-01 REV A March 2, 2009
ICS843003I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
3C. O
UTPUT
B
ANK
A C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA
÷1
÷2
÷3
÷4
T
ABLE
3D. O
UTPUT
B
ANK
B C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Outputs
QBx
÷2
÷4
÷5
÷8
T
ABLE
3E. F
EEDBACK
D
IVIDER
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_DIV
0
1
Feedback Divide
÷2 5
÷32
Disabled
REF_CLK
Enabled
OEA/B
nQA0,
nQB0:nQB1
QA0,
QB0:QB1
F
IGURE
1. OE T
IMING
D
IAGRAM
T
ABLE
3F. OEA S
ELECT
F
UNCTION
T
ABLE
Inputs
OEA
0
1
QA0
LOW
Active
Outputs
nQA0
HIGH
Active
T
ABLE
3G. OEB S
ELECT
F
UNCTION
T
ABLE
Inputs
OEB
0
1
LOW
Active
Outputs
QB0:QB1
nQB0:nQB1
HIGH
Active
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843003AGI-01 REV A March 2, 2009
ICS843003I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_A, B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
150
20
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
REF_CLK, MR, FB_DIV
DIV_SELA0, DIV_SELA1,
DIV_SELB0, DIV_SELB1,
VCO_SEL, XTAL_SEL,
OEA, OEB
REF_CLK, MR, FB_DIV
DIV_SELA0, DIV_SELA1,
DIV_SELB0, DIV_SELB1,
VCO_SEL, XTAL_SEL,
OEA, OEB
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IH
I
IL
Input
Low Current
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_A/B
- 1.4
V
CCO_A/B
- 2.0
0.6
Typical
Maximum
V
CCO_A/B
- 0.9
V
CCO_A/B
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_A/B
- 2V.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843003AGI-01 REV A March 2, 2009
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

843003AGI-01T Related Products

843003AGI-01T 843003AGI-01
Description Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts 24 24
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0
length 7.8 mm 7.8 mm
Humidity sensitivity level 1 1
Number of terminals 24 24
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Maximum output clock frequency 680 MHz 680 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP24,.25 TSSOP24,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 225 225
power supply 3.3 V 3.3 V
Master clock/crystal nominal frequency 27.2 MHz 27.2 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum slew rate 150 mA 150 mA
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 4.4 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER

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