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EPSA23BBJD-36.864MTR

Description
CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT
CategoryPassive components    oscillator   
File Size796KB,10 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric View All

EPSA23BBJD-36.864MTR Overview

CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT

EPSA23BBJD-36.864MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerECLIPTEK
Reach Compliance Codecompliant
Other featuresPOWER DOWN; ENABLE/DISABLE FUNCTION; TR, 7 INCH
maximum descent time3 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Nominal operating frequency36.864 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load15 pF
physical size5.0mm x 3.2mm x 1.3mm
longest rise time3 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Ecliptek | EPSA23 Series Oscillator
http://www.ecliptek.com/oscillators/EPSA23/
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| 714-433-1200 |
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EPSA23 Series Oscillator
Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount
(SMD)
2011/65 +
2015/863
168 SVHC
Revision D 02/27/2015
Electrical Specifications
Nominal Frequency
2.000MHz to 200.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability
(Inclusive of all conditions: Frequency Stability over the Operating
Temperature Range, Supply Voltage Change, Output Load Change,
First Year Aging at 25°C, Shock, and Vibration)
±50ppm Maximum
-40°C to +85°C
3.3V
DC
±10%
-0.5V
DC
to +4.2V
DC
15mA Maximum
23mA Maximum
27mA Maximum
30mA Maximum
166MHz
40mA Maximum
200MHz
over
over
over
over
Nominal
Nominal
Nominal
Nominal
Frequency
Frequency
Frequency
Frequency
of
of
of
of
2MHz to 25MHz
25.000001MHz to 50MHz
50.000001MHz to 100MHz
100.000001MHz to
Operating Temperature Range
Supply Voltage (V
DD
)
Maximum Supply Voltage
Input Current
over Nominal Frequency of 166.000001MHz to
Output Voltage Logic High (V
OH
)
IOH=-8mA
90% of V
DD
Minimum
IOL=+8mA
10% of V
DD
Maximum
Measured at 50% of waveform
50 ±5(%)
Measured at 10% to 90% of Waveform
3nSec Maximum
15pF Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
Power Down (Disabled Output: High Impedance)
70% of V
DD
Minimum or No Connection to Enable Output, 30% of V
DD
Maximum to Disable Output
70% of V
DD
Minimum or No Connection to Enable Output, 30% of V
DD
Maximum to Disable Output
100nSec Maximum
3mSec Maximum
Unloaded; Pad 1 = Ground
10 A Maximum (Power Down)
Output Voltage Logic Low (V
OL
)
Duty Cycle
Rise Time/Fall Time
Load Drive Capability
Output Logic Type
Output Control Function
Power Down Input Voltage (Vih and Vil)
Tri-State Input Voltage (Vih and Vil)
Power Down Output Disable Time
Power Down Output Enable Time
Standby Current
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