FemtoClock
®
SAS/SATA Clock Generator
ICS843441
DATA SHEET
General Description
The ICS843441 is a low jitter, high performance clock generator. The
ICS843441 is designed for use in applications using the SAS and
SATA interconnect. The ICS843441 uses an external, 25MHz,
parallel resonant crystal to generate four selectable output
frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon
based approach provides excellent frequency stability and reliability.
The ICS843441 features down and center spread spectrum (SSC)
clocking techniques.
Features
•
•
•
•
•
•
•
Output Frequency
(MHz)
75, 100, 150, 300
75
100
150
300
Designed for use in SAS, SAS-2, and SATA systems
Center (±0.33%) Spread Spectrum Clocking (SSC)
Down (-0.30% or -0.60%) SSC
Better frequency stability than SAW oscillators
One differential 3.3V LVPECL output
Crystal oscillator interface designed for 25MHz
(C
L
= 18pF) frequency
External fundamental crystal frequency ensures high reliability
and low aging
Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
Output frequency is tunable with external capacitors
RMS phase jitter: 1.33ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature available upon request
Available in lead-free (RoHS 6) package
Additional Ordering Information
Part/Order Number
843441AG
843441AM-75
843441AM-100
843441AM-150
843441AM-300
Package
16 TSSOP
8 SOIC
8 SOIC
8 SOIC
8 SOIC
•
•
•
•
•
•
•
Block Diagrams
XTAL
_IN
Pin Assignments
FemtoClock
Q
nQ
25MHz
XTAL
XTAL
_OUT
OSC
PLL
SSC_SEL(1:0)
Pulldown:Pulldown
SSC Output
Control Logic
8 - Lead SOIC
F_SEL(1:0)
nPLL_SEL
Pullup : Pulldown
Pulldown
ICS843441
8-Lead SOIC, 150 Mil
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
V
EE
nPLL_SEL
nQ
Q
V
CC
F_SEL0
V
CC
XTAL
_IN
25MHz
XTAL
XTAL
_OUT
OSC
FemtoClock
PLL
0
1
00 = 75MHz
01 = 100MHz
10 = 150MHz
(default)
11 = 300MHz
Q
nQ
XTAL_OUT
XTAL_IN
SSC_SEL0
nc
nc
nc
SSC_SEL1
SSC_SEL(1:0)
Pulldown: Pulldown
SSC Output
Control Logic
16- Lead TSSOP
ICS843441
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS843441AG REVISION A MAY 18, 2011
1
©2011 Integrated Device Technology, Inc.
ICS843441 Data Sheet
FEMTOCLOCK
®
SAS/SATA CLOCK GENERATOR
Table 1A. Pin Descriptions (SOIC Package)
Number
1,
2
3,
4
5
6, 7
8
Name
XTAL_OUT,
XTAL_IN
SSC_SEL0,
SSC_SEL1
V
CC
Q, nQ
V
EE
Input
Input
Power
Output
Power
Type
Pullup
Pulldown
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Power supply pin.
Differential clock outputs. LVPECL interface levels.
Negative supply pin.
NOTE:
Pullup/Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 1B. Pin Descriptions (TSSOP Package)
Number
1, 15
2,
3
4,
8
5, 6, 7
9, 11
10
12, 13
14
16
Name
V
EE
XTAL_OUT,
XTAL_IN
SSC_SEL0,
SSC_SEL1
nc
V
CC
F_SEL0
Q, nQ
nPLL_SEL
F_SEL1
Power
Input
Input
Unused
Power
Input
Output
Input
Input
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Type
Description
Negative supply pins.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
No connect pins.
Power supply pins.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
PLL Bypass pin. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
NOTE:
Pullup/Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS843441AG REVISION A MAY 18, 2011
2
©2011 Integrated Device Technology, Inc.
ICS843441 Data Sheet
FEMTOCLOCK
®
SAS/SATA CLOCK GENERATOR
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Inputs
SSC_SEL1
0 (default)
0
1
1
SSC_SEL0
0 (default)
1
0
1
Mode
SSC Off
0.60% Down-spread
0.30% Down-spread
0.33% Center-spread
Table 3B. F_SEL[1:0] Function Table
Inputs
F_SEL1
0
0
1 (default)
1
F_SEL0
0
1
0 (default)
1
Output Frequency (MHz)
75
100
150
300
Table 3B applicable only for 16 Lead TSSOP package.
ICS843441AG REVISION A MAY 18, 2011
3
©2011 Integrated Device Technology, Inc.
ICS843441 Data Sheet
FEMTOCLOCK
®
SAS/SATA CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
, (LVCMOS)
XTAL_IN
Other Inputs
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
16 Lead TSSOP
8 Lead SOIC
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
81.2°C/W (0 mps)
96.0°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
66
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
F_SEL1
Input
High Current
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
F_SEL1
I
IL
Input
Low Current
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
0.9
Units
V
V
V
NOTE 1: Output termination with 50Ω to V
CC
– 2V.
ICS843441AG REVISION A MAY 18, 2011
4
©2011 Integrated Device Technology, Inc.
ICS843441 Data Sheet
FEMTOCLOCK
®
SAS/SATA CLOCK GENERATOR
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
Parameter
Test Conditions
F_SEL(1:0) = 00
f
OUT
Output Frequency
F_SEL(1:0) = 01
F_SEL(1:0) = 10
F_SEL(1:0) = 11
75MHz,
Integration Range: 12kHz – 20 MHz
RMS Phase Jitter
(Random); NOTE 1
100MHz,
Integration Range: 12kHz – 20MHz
150MHz,
Integration Range: 12kHz – 20MHz
300MHz,
Integration Range: 12kHz – 20MHz
75MHz, SSC Off
tjit(per)
Period Jitter, RMS;
NOTE 2, 3
100MHz, SSC Off
150MHz, SSC Off
300MHz, SSC Off
75MHz, SSC Off
tjit(cc)
Cycle-to-Cycle Jitter:
NOTE 3
100MHz, SSC Off
150MHz, SSC Off
300MHz, SSC Off
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
45
Minimum
Typical
75
100
150
300
1.33
1.39
1.36
1.37
4.15
4.05
4.15
4.25
31
31
31
31
700
55
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
tjit(Ø)
NOTE: Using a 25MHz, 18pF quartz crystal.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: Refer to Application Section for peak-to-peak jitter calculations.
NOTE 3: Tested per JEDEC 65B.
ICS843441AG REVISION A MAY 18, 2011
5
©2011 Integrated Device Technology, Inc.
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