IBM Microelectronics
1394 Host Link Layer Controller
Enables IEEE 1394 standard PCI performance
Highlights
• Fully IEEE 1394-1995 compatible
• Four bidirectional (transmit/receive)
isochronous DMA contexts
• Supports up to 63 isochronous channels
in transmit operation
• Uses Descriptor Based DMA (DB-DMA)
context structure
• Two asynchronous DMA contexts for
transmit
• One asynchronous DMA context for
inbound packets
• Self-ID packets automatically routed to a
single designated host memory buffer
• Programmable 1K byte transmit FIFO and
1K byte receive FIFO
• Data rates: S100, S200, S400 Mb/s
• Supports ‘Isolation Barrier’ and IBM’s
‘Dynamic Termination’ modes on the
PHY/Link interface
• Cycle Master capable
• External configuration ROM interface
• PCI 2. interface
1
–
Supports cache line commands
(memory write & invalidate, memory
read line, memory read multiple)
–
Supports long burst PCI transactions
–
No wait states
Product Overview
The IBM 21S650PFA is a high perfor-
mance IEEE 1394 Link Layer Controller
with a PCI system interface. It is capable
of operating as a PCI master or slave and
supports long burst PCI transactions at
up to 33MHz. Its physical layer interface
supports data rates of 100 Mbit/s, 200
Mbit/s and 400 Mbit/s. Furthermore, a
DMA engine is incorporated to minimize
CPU intervention during packet transmis-
sion and reception.
In addition, an interface to an external
configuration ROM is provided, allowing
system designers to store 1394 and PCI
configuration information. The IBM
21S650PFA also has features to support the
transaction and bus management layers.
Figure 1 describes a typical system that
uses the IBM 1394 Link Controller.The PHY
chip handles the physical layer protocol
and interface to the 1394 serial bus cables.
tional channels for isochronous receive/
transmit.
Asynchronous Transmission
The IBM 21S650PFA can transmit and
receive all of the defined 1394 packet
formats. Packets to be transmitted are read
from host memory and received packets
are written to host memory using DMA. To
avoid deadlock conditions, two DMA
contexts are used; one for request packets
and one for response packets. In addition,
the link supports automatic retry of packet
transmission following the reception of a
‘busy acknowledge.’
All received packets, with the exception of
self-ID packets, are directed to the
General Receive context. In compliance
with the OHCI specification, self-ID
packets, which are received during the
self-identification phase of bus initializa-
tion, are automatically routed to a single
designated host memory buffer. Each
time bus initialization occurs, the new self-
CPU
DMA Engine
The IBM 21S650PFA incorporates a DMA
engine to fetch packets from the system
memory and transmit them to the 1394
bus, and to write received packets to the
system memory. The industry standard
Descriptor Based DMA (DB-DMA)
structure is used. Each asynchronous and
isochronous context is comprised of a
buffer descriptor list called a DMA context
program, stored in main memory. Buffers
are specified within the DMA context
program by DMA descriptors.
IBM's Link supports seven DMA contexts;
two for asynchronous transmit, one for
asynchronous receive and four bidirec-
Host
Bridge
DRAM
PCI Bus
PCI
Component
1394 Link
Layer
Controller
PHY
1394 Bus
1394
Device
1394
Device
1394 Bus
1394
Device
1394
Device
Figure 1
ID packets will be written into the self-ID
buffer, overwriting the old self-ID packets.
Isochronous Transmission
The IBM 21S650PFA supports 4 isochro-
nous DMA contexts, each of which can be
programmed for transmit or receive
operation. In transmit, the channel program
consists of a list of isochronous packets
that should be transmitted. Each DMA
context can be used to transmit data on up
to 63 isochronous channels. In the case of
a cycle lost or an underrun condition, the
link discards the packets of the current
isochronous cycle and skips to the
packets for the next isochronous cycle.
Isochronous packets in the receive FIFO
are processed by the DMA context which
is configured to receive their respective
isochronous channel number. Each
context can be configured to strip packet
headers or include the headers and
trailers when moving the packets into the
buffers. Additionally, in accordance with
the OHCI specification, each DMA
context can be configured to concat-
enate multiple packets into its buffers
(bufferfill mode) or to place just a single
packet into each buffer (packet per-buffer
mode). The activation of the isochronous
DMA contexts can also be synchronized
to a certain cycle or ‘sync’ value.
Additionally, IBM's Link controller can be
programmed to be the Isochronous Cycle
Master. In this mode it generates the cycle
start packet every 125
µsec.
© International Business Machines Corporation 1997
Printed in the United States of America
10-97
All Rights Reserved
* Indicates a trademark or registered trademark of the
International Business Machines Corporation.
** All other products and company names are
trademarks or registered trademarks of their
respective holders.
The information contained in this document is subject
to change without notice. The products described in
this document are NOT intended for use in implanta-
tion or other life support applications where
malfunction may result in injury or death to persons.
The information contained in this document does not
affect or change IBM’s product specifications or
warranties. Nothing in this document shall operate as
an express or implied license or indemnity under the
intellectual property rights of IBM or third parties. All
the information contained in this document was
obtained in specific environments, and is presented
as an illustration. The results obtained in other
operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT
IS PROVIDED ON AN “AS IS” BASIS. In no event will
IBM be liable for any damages arising directly or
indirectly from any use of the information contained
in this document.
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY
12533-6531
The IBM home page can be found at:
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at:
http://www.chips.ibm.com
Specifications
0.45µ CMOS technology
3.3V power supply
5.0V tolerant I/Os
144 pin package
108
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GND
PCI_IDSEL_DI2
GND
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_C/BE#1
VDD
PCI_PAR
PCI_SERR#
GND
PCI_PERR#
PCI_STOP#
VDD
PCI_DEVSEL#
PCI_TRDY#
GND
PCI_IRDY#
VDD
PCI_FRAME#
GND
PCI_C/BE#2
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
VDD
VDD
PCI_C/BE#0
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
GND
VDD
GND
RESERV
GND
TEST
GND
VDD
ISOBAR_TEST#
GND
GND
ROM_CS#
ROM_ADD0
VDD
ROM_ADD1
ROM_ADD2
ROM_ADD3
ROM_ADD4
ROM_ADD5
ROM_ADD6
GND
ROM_ADD7
ROM_ADD8
ROM_ADD9
ROM_ADD10
GND
109
110
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144
IBM21S650PFA (88H2785)
20mm
◊20
mm
144 pin LQFP
GND
PCI_C/BE#3
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
VDD
PCI_REQ#
GND
PCI_GNT#
VDD
GND
GND
PCI_CLK
VDD
GND
PCI_RST#
GND
PCI_INT#
VDD
CYCLEIN_DI1
GND
VDD
RESERV
PHY_LREQ
PHY_CTL1
PHY_CTL0
GND
PHY_DATA7
PHY_DATA6
PHY_DATA5
VDD
VDD
ROM_ADD11
ROM_ADD12
ROM_ADD13
ROM_ADD14
ROM_ADD15
GND
PHY_DTE
GND
VDD
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
VDD
ROM_DATA7
GND
GND
RESERV
PHY_ISOBAR
VDD
CYCLEOUT
GND
PHY_LPS
VDD
PHY_CLK
GND
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
GND
1
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Figure 2
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