S25FL512SDSMFM011 datasheet, PDF

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S25FL512SDSMFM011: DescriptionFlash, 128MX4, PDSO16, SOP-16; Categorystorage storage; File Size4MB，136 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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S25FL512SDSMFM011 Overview

Flash, 128MX4, PDSO16, SOP-16

S25FL512SDSMFM011 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
package instruction	SOP,
Reach Compliance Code	compliant
Other features	ITS ALSO CONFIGURABLE AS 512MX1
Spare memory width	1
Maximum clock frequency (fCLK)	80 MHz
JESD-30 code	R-PDSO-G16
length	10.3 mm
memory density	512753664 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	16
word count	64094208 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	3 V
Filter level	AEC-Q100; TS 16949
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm

S25FL512SDSMFM011 Preview

S25FL512S

512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory

Features



CMOS 3.0 Volt Core with Versatile I/O



Serial Peripheral Interface with Multi-I/O



Density

– 512 Mbits (64 Mbytes)



Serial Peripheral Interface (SPI)

– SPI Clock polarity and phase modes 0 and 3

– Double Data Rate (DDR) option

– Extended Addressing: 32-bit address

– Serial Command set and footprint compatible with S25FL-

S25FL-K, and S25FL-P SPI families

– Multi I/O Command set and footprint compatible with

S25FL-P SPI family



READ Commands

– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad

DDR

– AutoBoot - power up or reset and execute a Normal or

Quad read command automatically at a preselected

address

– Common Flash Interface (CFI) data for configuration

information.



Programming (1.5 MB/s)

– 512-byte Page Programming buffer

– Quad-Input Page Programming (QPP) for slow clock

systems

– Automatic ECC -internal hardware Error Correction Code

generation with single bit error correction



Erase (0.5 to 0.65 MB/s)

– Uniform 256-kbyte sectors



Cycling Endurance

– 100,000 Program-Erase Cycles, minimum



Data Retention

– 20 Year Data Retention, minimum



Security features

– One Time Program (OTP) array of 1024 bytes

– Block Protection:

– Status Register bits to control protection against

program or erase of a contiguous range of sectors.

– Hardware and software control options

– Advanced Sector Protection (ASP)

– Individual sector protection controlled by boot code or

password



Cypress

65 nm MirrorBit

Technology with Eclipse

™

Architecture



Core Supply Voltage: 2.7 V to 3.6 V



I/O Supply Voltage: 1.65 V to 3.6 V

– SO16 and FBGA packages



Temperature Range:

– Industrial (–40 °C to +85 °C)

– Industrial Plus (–40 °C to +105 °C)

– Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)

– Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)

– Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)



Packages (all Pb-free)

– 16-lead SOIC (300 mil)

– BGA-24 6 × 8 mm

– 5 × 5 ball (FAB024) and 4 × 6 ball (FAC024) footprint

options

– Known Good Die and Known Tested Die

Cypress Semiconductor Corporation

Document Number: 001-98284 Rev. *L

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 22, 2017

S25FL512S

Logic Block Diagram

CS#

SCK

SI/IO0

SO/IO1

I/O

WP#/IO2

HOLD#/IO3

RESET#

Data Path

Control

Logic

X Decoders

SRAM

MirrorBit Array

Y Decoders

Data Latch

Performance Summary

Maximum Read Rates with the Same Core and I/O Voltage (V

= V

= 2.7 V to 3.6 V)

Command

Read

Fast Read

Dual Read

Quad Read

Clock Rate (MHz)

133

104

Mbps

6.25

16.6

Maximum Read Rates with Lower I/O Voltage (V

= 1.65 V to 2.7 V, V

= 2.7 V to 3.6 V)

Command

Read

Fast Read

Dual Read

Quad Read

Clock Rate (MHz)

Mbps

6.25

8.25

16.5

Maximum Read Rates DDR (V

= V

= 3 V to 3.6 V)

Command

Fast Read DDR

Dual Read DDR

Quad Read DDR

Clock Rate (MHz)

Mbps

Typical Program and Erase Rates

Operation

Page Programming (512-byte page buffer - Uniform Sector Option)

256-kbyte Logical Sector Erase (Uniform Sector Option)

kbytes/s

1500

500

Document Number: 001-98284 Rev. *L

Page 2 of 136

S25FL512S

Current Consumption

Operation

Serial Read 50 MHz

Serial Read 133 MHz

Quad Read 104 MHz

Program

Erase

Standby

Current (mA)

16 (max)

33 (max)

61 (max)

100 (max)

0.07 (typ)

Document Number: 001-98284 Rev. *L

Page 3 of 136

S25FL512S

Contents

Features.................................................................................

Logic Block Diagram............................................................

Performance Summary

........................................................ 2

1.1

1.2

1.3

1.4

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

3.1

3.2

3.3

3.4

3.5

4.1

4.2

4.3

4.4

4.5

5.1

5.2

5.3

5.4

5.5

6.1

6.2

6.3

Overview

.......................................................................

General Description .......................................................

Migration Notes..............................................................

Glossary.........................................................................

Other Resources............................................................

7.1

7.2

7.3

7.4

7.5

7.6

8.1

8.2

8.3

8.4

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

Overview....................................................................... 44

Flash Memory Array...................................................... 44

ID-CFI Address Space .................................................. 44

JEDEC JESD216 Serial Flash Discoverable Parameters

(SFDP) Space............................................................... 45

OTP Address Space ..................................................... 45

Registers....................................................................... 46

Data Protection

........................................................... 55

Secure Silicon Region (OTP)........................................ 55

Write Enable Command................................................ 55

Block Protection ............................................................ 55

Advanced Sector Protection ......................................... 57

Commands

.................................................................. 61

Command Set Summary............................................... 62

Identification Commands .............................................. 67

Read Memory Array Commands .................................. 78

Program Flash Array Commands ................................. 92

Erase Flash Array Commands...................................... 95

One Time Program Array Commands .......................... 99

Advanced Sector Protection Commands .................... 100

Reset Commands ....................................................... 104

Embedded Algorithm Performance Tables ................. 105

Hardware Interface

Signal Descriptions

..................................................... 9

Input/Output Summary................................................... 9

Address and Data Configuration.................................. 10

RESET# ....................................................................... 10

Serial Clock (SCK) ....................................................... 10

Chip Select (CS#) ........................................................ 10

Serial Input (SI) / IO0 ................................................... 11

Serial Output (SO) / IO1............................................... 11

Write Protect (WP#) / IO2 ............................................ 11

Hold (HOLD#) / IO3 ..................................................... 11

Core Voltage Supply (V

) .......................................... 12

Versatile I/O Power Supply (V

) ................................. 12

Supply and Signal Ground (V

) ................................. 12

Not Connected (NC) .................................................... 12

Reserved for Future Use (RFU)................................... 12

Do Not Use (DNU) ....................................................... 12

Block Diagrams............................................................ 13

Signal Protocols.........................................................

SPI Clock Modes .........................................................

Command Protocol ......................................................

Interface States............................................................

Configuration Register Effects on the Interface ...........

Data Protection ............................................................

Electrical Specifications............................................

Absolute Maximum Ratings .........................................

Thermal Resistance .....................................................

Operating Ranges........................................................

Power-Up and Power-Down ........................................

DC Characteristics .......................................................

Timing Specifications................................................

Key to Switching Waveforms .......................................

AC Test Conditions ......................................................

Reset............................................................................

SDR AC Characteristics...............................................

DDR AC Characteristics ..............................................

Physical Interface

......................................................

SOIC 16-Lead Package ...............................................

FAB024 24-Ball BGA Package ....................................

FAC024 24-Ball BGA Package ....................................

10. Data Integrity

............................................................. 106

10.1 Erase Endurance ........................................................ 106

10.2 Data Retention ............................................................ 106

11. Software Interface Reference

.................................. 107

11.1 Command Summary ................................................... 107

11.2 Serial Flash Discoverable Parameters (SFDP) Address

Map............................................................................. 109

11.3 Device ID and Common Flash Interface (ID-CFI) Address

Map............................................................................. 112

11.4 Registers..................................................................... 127

11.5 Initial Delivery State .................................................... 130

Ordering Information

................................................ 131

13. Revision History........................................................

133

Document History Page .................................................... 133

Sales, Solutions, and Legal Information ......................... 137

Worldwide Sales and Design Support.......................... 137

Products ....................................................................... 137

PSoC® Solutions ......................................................... 137

Cypress Developer Community.................................... 137

Technical Support ........................................................ 137

Software Interface

Address Space Maps.................................................

Page 4 of 136

Document Number: 001-98284 Rev. *L

S25FL512S

1. Overview

1.1 General Description

The Cypress S25FL512S device is a flash nonvolatile memory product using:



MirrorBit technology - that stores two data bits in each memory array transistor

Eclipse architecture - that dramatically improves program and erase performance

65 nm process lithography

This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single

I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple

width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands

for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.

The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be programmed in one

operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates

supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,

asynchronous, NOR flash memories while reducing signal count dramatically.

The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a variety of embedded

applications. It is ideal for code shadowing, XIP, and data storage.

1.2 Migration Notes

1.2.1

Features Comparison

The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families.

Table 1. FL Generations Comparison

Parameter

Technology Node

Architecture

Release Date

Density

Bus Width

Supply Voltage

Normal Read Speed (SDR)

Fast Read Speed (SDR)

Dual Read Speed (SDR)

Quad Read Speed (SDR)

Fast Read Speed (DDR)

Dual Read Speed (DDR)

Quad Read Speed (DDR)

Program Buffer Size

Erase Sector Size

Parameter Sector Size

Sector Erase Time (typ.)

Page Programming Time (typ.)

OTP

Advanced Sector Protection

Auto Boot Mode

FL-K

90 nm

Floating Gate

In Production

4 Mb - 128 Mb

x1, x2, x4

2.7 V - 3.6 V

6 MB/s (50 MHz)

13 MB/s (104 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

—

256B

4 kB / 32 kB / 64 kB

4 kB

30 ms (4 kB), 150 ms (64 kB)

700 µs (256B)

768B (3 x 256B)

FL-P

90 nm

MirrorBit

In Production

32 Mb - 256 Mb

x1, x2, x4

2.7 V - 3.6 V

5 MB/s (40 MHz)

13 MB/s (104 MHz)

20 MB/s (80 MHz)

40 MB/s (80 MHz)

—

256B

64 kB / 256 kB

4 kB

500 ms (64 kB)

1500 µs (256B)

506B

FL-S

65 nm

MirrorBit Eclipse

In Production

512 Mb

x1, x2, x4

2.7 V - 3.6 V / 1.65 V - 3.6 V V

6 MB/s (50 MHz)

17 MB/s (133 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

20 MB/s (80 MHz)

40 MB/s (80 MHz)

80 MB/s (80 MHz)

512B

256 kB

—

520 ms (256 kB)

340 µs (512B)

1024B

Yes

Document Number: 001-98284 Rev. *L

Page 5 of 136

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Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
package instruction	SOP,	SOP,	SOP,	SOP, SOP16,.4
Reach Compliance Code	compliant	compliant	compliant	compli
Spare memory width	1	1	1	1
Maximum clock frequency (fCLK)	80 MHz	80 MHz	80 MHz	80 MHz
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
length	10.3 mm	10.3 mm	10.3 mm	10.3 mm
memory density	512753664 bit	512753664 bit	512753664 bit	512753664 bi
Memory IC Type	FLASH	FLASH	FLASH	FLASH
memory width	8	8	8	8
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
word count	64094208 words	64094208 words	64094208 words	64094208 words
character code	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	105 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	64MX8	64MX8	64MX8	64MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Parallel/Serial	SERIAL	SERIAL	SERIAL	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Programming voltage	3 V	3 V	3 V	3 V
Filter level	AEC-Q100; TS 16949	AEC-Q100; TS 16949	AEC-Q100; TS 16949	AEC-Q100; TS 16949
Maximum seat height	2.65 mm	2.65 mm	2.65 mm	2.65 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm
Other features	ITS ALSO CONFIGURABLE AS 512MX1	ITS ALSO CONFIGURABLE AS 512MX1	ITS ALSO CONFIGURABLE AS 512MX1	-

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