FM3570M20 datasheet, PDF - EEWORLD Datasheet

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FM3570M20: DescriptionSPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, PLASTIC, SOP-20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size775KB，9 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, PLASTIC, SOP-20

FM3570M20 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Rochester Electronics
Parts packaging code	SOIC
package instruction	SOP,
Contacts	20
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	12.8 mm
Humidity sensitivity level	NOT SPECIFIED
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	COMMERCIAL
Maximum seat height	2.65 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT

FM3570M20 Preview

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FM3570 CPU CONFIGURATION CONTROLLER

Preliminary

March 2001

FM3570

CPU CONFIGURATION CONTROLLER

General Description

The Fairchild FM3570 replaces the CPU motherboard’s configu-

ration switches with an electronic implementation consisting of a

4/5-bit multiplexed, 1-bit latched port, standard 2-wire bus inter-

face, and non-volatile latches.

The FM3570 multiplexes the I-port input signals with two internal

non-volatile registers that can be loaded through the serial port.

The multiplexer is selected via the serial port and defaults to the

I-port upon power-up. Pull-up resistors are provided on the input

port to accommodate connections to open-drain outputs and to

eliminate the need for external resistors. The device has open-

drain outputs for easy interface to devices with different V

levels.

The serial port is an IIC compatible slave-only interface and

supports both 100kbit and 400kbit modes of operation. The port

is used to read the I-Port, write data to the internal non-volatile

registers and select whether the I-port or one of the internal non-

volatile registers is output to the Y-port. The FM3570 is fabricated

with advanced CMOS technology to achieve high density and low

power operation.

Features

Extended Operating Voltage Range 3.0V-5.5V

IIC Compatible Slave Interface.

ESD performance: Human body model > 2000V

Choice of 2.5V Outputs or Open-Drain Outputs

Block Diagram

Non_Mux_Out

I[4:0]

Y[4:0]

Mux1

SOPRA

Mux2

SOPRB

MXSB, MXSA

IIC Read Logic

Mux3

Control Logic

MUXSEL

OVRD

SDA

SCL

IIC

Interface

Shift

Slave Address

ASEL

Comparator

Start/Stop

Logic

FM3570 Rev. A

www.fairchildsemi.com

FM3570 CPU CONFIGURATION CONTROLLER

Ordering Code

3570

XXXX

Blank

Tube

Tape & Reel

M20

MT20

20-Pin SO Package Option

20-Pin TSSOP Package Option

Order Number

FM3570MT20

FM3570MT20X

FM3570M20

FM3570M20X

Package Number

MTC20

M20B

Package Description

20-Pin TSSOP

20-Pin TSSOP T & R

20 Pin SO

20 Pin SO T & R

For all other combinations, check with Fairchild Marketing/Sales

Pin Connection Diagram

20-Pin Packages

FM3570

SCL

SDA

OVRD

Level

GND

ASEL

Non_Mux_Out

MUXSEL

Pin Description

Pin Name

I [0:4]

Y [0:4]

SCL

OVRD

Non_mux_out

MUXSEL

EPV

ASEL

SDA

Description

Data Inputs w/Pullups (10K-40K)

Open-Drain Data Outputs

Serial Port Clock Input (120K pullup)

Override Input. Sets all outputs to 0

Write Protect Input

Non-Multiplexed Output

Multiplexer Select Input

I Port Pull-up Resistor Voltage

Address Select Input

Serial Port Data I/O (120K pull-up)

FM3570 Rev. A

www.fairchildsemi.com

FM3570 CPU CONFIGURATION CONTROLLER

Functional Description

The FM3570 block diagram is shown in Figure 1. The device has

two primary functional modes of operationi and an additional

mode for programming the device.

Serial Output Port Register A(SOPRA) Address: 00H

- A read/

write register that contains the new value to be written to output

Port-Y and the multiplexer select bit.

Serial Output Port Register B(SOPRB) Address: 01H

- A read/

write register that contains the new value to be written to output

Port-Y and the multiplexer select bit.

Parallel Input Port Register (PIPR) Address: 02H

- A read-only

Operational Modes

During standard operation, the device will either pass an address

to the Y-Port from the I-Port or from an internally programmed

value.

The I-port values are generated from the motherboard of the

system and may be hardwired or driven by another device. Pull-

up resistors are provided on the device to accommodate this

device being driven by open-drain output drivers. The voltage

level to which the I-port is pulled up to is determined by the voltage

on the EPV pin. The device expects standard CMOS input signals.

The the non-multiplexed output is always at CMOS levels. The

OVRD (override) input, when set to 0, will cause all the outputs to

be set to 0. The WP signal, if set to logic 1, will prevent data from

being written to the non-volatile register.

The MUXSEL input, when set to logic 0, will select the data from

the non-volatile register to drive on the Y0-4 outputs. if set to logic

1, the data from the inputs are selected instead. the non_mux_out

latch is transparent when the MUXSEL signal is at logic 0, and will

latch when the MUXSEL is in a logic 1 state.

Serial Output Port Register (SOPR)

(Address 000b and 001b)

MXSB MXSA

NMO

Data Field

b7-b6 - Multiplexer Select Bits (MXSB, MXSA)

00 - Multiplexer passes the SOPR(A).

01 - Multiplexer passer the SOPR(B).

10 - Multiplexer defaults to passing the I-Port Value.

b5, b3-b0 - Data Field. New value to be output through the

multiplexer.

NMO - Non-multiplexed output from internal non-volatile bit.

Output Port: Y0-Y4

The output port is an open-drain output to allow for easy connec-

tion to devices running at different voltage levels. The port is

always active and either passes the value on the I-Port or the value

in the Serial output port (SOPR). Changing the Mux Path is

accomplished by writing to b7 of the Serial Input Port Register.

SOPR-b7 defaults to a value of zero at power up and the default

path is from the I-port though to the output port. The multiplexer

only updates when an IIC stop condition is observed.

Parallel Input Port Register (PIPR)

(Address 002b)

Address Field

Data Field

b7-b5 - Address field. Value is always 000

b4-b0 - Data Field. Value is equal to the value on the I-Port.

The external Port Register captures the value on the I-Port. Data

is latched into this register on the first clock after a start condition

is seen. This insures that a valid value will always be in this register

if it is read. This register is a-read only register with respect to the

IIC port.

The FM3570 has 3 registers in total. These registers are made up

of a combination of read-only, write-only and read/write bits. The

two registers are listed below.

FM3570 Rev. A

www.fairchildsemi.com

FM3570 CPU CONFIGURATION CONTROLLER

OVRD

MUXSEL

MXSB

MXSA

Mux_

outputs

all 0’s

Mux_

inputs

Mux_

inputs

Note 2

Note 1

From

Non-

volatile

(SOPRA)

Do not use this

c ombination

From

From No n-

Non-

volatile

(SOPRB)

Mux_i

From No n-

nputs

volatile

(SOPRA or

SOPRB)

No n_mux_

ouput

all 0’s

latched

NMO

(see Note 1)

latched

NMO

(see Note 1)

From No n-

volatile

(SOPRA)

The IIC protocol uniquely defines START and STOP conditions.

A START condition is defined as a HIGH to LOW transition of the

SDA signal while SCL is HIGH. A STOP condition is defined as a

LOW to HIGH transition of the SDA signal while SCL is HIGH.

These are shown in Figure 2.

Device Addressing

The device uses 7-bit IIC addressing.The address has been

defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the

ASEL input is ‘0’. The address byte is the first byte of data sent after

a start condition. This is the only address that this device will

respond to. The device will not respond to the general call address

0000 000.

Reading from the Registers

Data can be read from both of the internal registers. All reads are non-

destructive and do not change the value in the register or the internal

state of the device. When a start condition is received with a read

request, both registers can be read out in the following sequence:

(1)

(2)

(3)

SOPRA: Serial Output Port Register A

SPORB: Serial Output Port Register B

PIPR: PORT-I Value

Note 1:

Latched NMO state will be the value present on the NMO output at the time

of the MUXSEL input transitioning from logic 0 to logic 1 state.

Note 2:

Output depends on previously selected state of MXSB and MXSA bits

written to device.

If so desired, only the SOPRA register can be read. This is

accomplished by issuing a stop command after the acknowledge

bit for the first byte is read. If no stop is issued, the device will output

the registers in the above sequence.

Multiplexer Logic

The output multiplexer logic determines what value is actually

output to the Y-port. The value that it output is dependent upon

b7-b6 of the SOPRA and SOPRB registers, as well as the

external MUXSEL and OVRD inputs. There is only one set of

MXS bits in the SOPRA and SOPRB registers. Regardless of

whether one writes to SPRA or SOPRB register for setting the

MXS bits, the result is the same. These same bits appear in

both the registers. If the MUXSEL is logic 0 and OVRD is logic

1, then, if b7, b6 is “10” then the value on the I-port is passed.

when b7 is “00” the value of the SOPRA register is passed on

the next IIC stop condition, and when b7 is “01” the value of the

SOPRB register is passed on the next IIC stop condition. If

MUXSEL is logic 1 and OVRD is logic 1, the input lines I0-4 are

used to drive the outputs. The above table describes all the

combinations.

Writing to the Registers

Data is written to the SOPR registers through the serial port

interface. When a write request is received with the Start Address

it is assumed that the intent is to write to the SOPR registers. The

value placed in the least 6 significant bits of the register contain the

new code to be placed in the SOPR A/B registers. The value of the

two most significant bits must contain the address of the destina-

tion register SOPRA or SOPRB.

The internal non-volatile latch takes about 10 ms to update its data.

The new data is reflected on the outputs after the internal non-volatile

latch is updated, if the corresponding select bits (MXSx, OVRD and

MUXSEL) are set to reflect the state of the non-volatile register.

IIC Interface

The IIC Interface is a standard slave interface. As a slave interface

the device will not generate its own clock. Data can be read from

and written into the device. Commands for reading and writing the

registers are generated by the IIC Master.

Slave

Address

1001110

SOPRA

R A Register

SOPRB

A Register

PIPR

A Register

A P

A 00bbbbbb A 00bbbbbb A 00bbbbbb A P

START and STOP Conditions

SDA

Slave

SOPRx

Address W A Register

1001110

A xxbbbbbb

A S

xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01

selects SOPRB

SCL

START

Condition

STOP

Condition

Repeated Start Condition

Slave

SOPRA

Slave

SOPRx

S Address R A Register A S Address W A Register A P

S 1001110 1 A 00bbbbbb A S 1001110 0

A xxbbbbbb A P

Figure 2. START & STOP Conditions

Figure 4

FM3570 Rev. A

www.fairchildsemi.com

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

FM3570M20 Related Products

	FM3570M20	FM3570MT20X
Description	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, PLASTIC, SOP-20	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, PLASTIC, TSSOP-20
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	Rochester Electronics	Rochester Electronics
Parts packaging code	SOIC	TSSOP
package instruction	SOP,	TSSOP,
Contacts	20	20
Reach Compliance Code	unknown	unknown
JESD-30 code	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e3	e3/e4
length	12.8 mm	6.5 mm
Humidity sensitivity level	NOT SPECIFIED	1
Number of terminals	20	20
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
Certification status	COMMERCIAL	COMMERCIAL
Maximum seat height	2.65 mm	1.2 mm
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN	MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	7.5 mm	4.4 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT	MICROPROCESSOR CIRCUIT

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