SN74ACT72221L50RJ datasheet, PDF

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SN74ACT72221L50RJ: Description1KX9 OTHER FIFO, 25ns, PQCC32, PLASTIC, LCC-32; Categorystorage storage; File Size997KB，24 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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SN74ACT72221L50RJ Overview

1KX9 OTHER FIFO, 25ns, PQCC32, PLASTIC, LCC-32

SN74ACT72221L50RJ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Maker	Rochester Electronics
Parts packaging code	QFJ
package instruction	PLASTIC, LCC-32
Contacts	32
Reach Compliance Code	unknown
Maximum access time	25 ns
period time	50 ns
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
memory density	9216 bit
memory width	9
Humidity sensitivity level	NOT SPECIFIED
Number of functions	1
Number of terminals	32
word count	1024 words
character code	1000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	COMMERCIAL
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED

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SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L

512

9, 1024

9, 2048

9, AND 4096

SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SCAS222 – FEBRUARY 1993 – REVISED JUNE 1993

Terminal Functions

TERMINAL

NAME

D0 – D8

GND

PAE

PAF

Q0 – Q8

RCLK

REN1,

REN2

VCC

WCLK

NO.

6 – 1,

32 – 30

16 – 24

10,

I/O

Data inputs

Empty-flag. When memory is empty, EF is low and further data reads are ignored by the device. When EF is

high, the memory is not empty and data reads are allowed. EF is synchronized to RCLK by one flip-flop.

Full-flag. When memory is full, FF is low and data writes are inhibited. FF is synchronized to WCLK by one

flip-flop.

Ground

Output-enable. Q0 – Q8 are in the high-impedance state when OE is high. Q0 – Q8 are active when OE is low.

Programmable almost-empty-flag. PAE is low when the FIFO is almost empty based on the value in its offset

Programmable almost-full-flag. PAF is low when the FIFO is almost full based on the value in its offset register.

The default value for the register is full – 7. PAF is synchronized to WCLK by one flip-flop.

Data outputs

Read-clock. A data read is performed by the low-to-high transition of RCLK when REN1 and REN2 are

asserted and EF is high.

Read-enable. Data is read from the FIFO on a low-to-high transition of RCLK when REN1 and REN2 are low

and EF is high.

Reset. When RS is set low, the read and write pointers are initialized to the first RAM location and the FIFO

is empty. FF and PAF are set high, and EF and PAE are set low. Each bit in the data output register is set low

by a device reset. The FIFO must be reset after power up before data is written.

Supply voltage

Write-clock. Data is written by the low-to-high transition of WCLK when WEN1 and WEN2/LD are asserted and

FF is high.

Write-enable 1. WEN1 is the only write enable terminal if the device is configured to have programmable flags.

Data is written on a low-to-high transition of WCLK when WEN1 is low and FF is high. If the FIFO is not

configured for programmable flags, data is written on a low-to-high transition of WCLK when WEN1 and WEN2

are asserted and FF is high.

Write-enable 2 / load. This is a dual-purpose input. The FIFO can have either two write enables or

programmable flags. To use WEN2/LD as a WEN2, WEN2/LD must be held high at reset. When WEN2 and

WEN1 are asserted and FF is high, a low-to-high transition of WCLK writes data. To use WEN2/LD as the LD

terminal, it must be held low at reset. In this case, LD is asserted low to write or read the programmable offset

registers.

DESCRIPTION

WEN1

WEN2/LD

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L

512

9, 1024

9, 2048

9, AND 4096

SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SCAS222 – FEBRUARY 1993 – REVISED JUNE 1993

detailed description

device reset

A reset is performed by taking the reset (RS) input low. This initializes both the write and read pointers to the

first memory location. After a reset, the full flag (FF) and programmable almost-full flag (PAF) are high and the

empty flag (EF) and programmable almost-empty flag (PAE) are low. Each bit in the data output register

(Q0 – Q8) is set low, and the flag offset registers are loaded with the default offset values. A FIFO must be reset

after power up before a write cycle is allowed.

The logic level on the dual-purpose input write enable 2 / load (WEN2/LD) during reset determines its function.

If WEN2/LD is high when RS returns high at the end of the reset cycle, the input is a second write enable (see

FIFO writes and reads) and the programmable flags (PAF, PAE) can only use the default values. If WEN2/LD

is low when RS returns high at the end of the reset cycle, the input is the load (LD) enable for writing and reading

flag offset registers (see flag programming).

FIFO writes and reads

Data is written to memory by a low-to-high transition of write clock (WCLK) when write enable 1 (WEN1) is low,

WEN2/LD is high, and FF is high. This stores D0 – D8 data in the dual-port SRAM and increments the write

pointer.

If no reads are performed after reset (RS = V

), FF is set low upon the completion of 512 writes to the

SN74ACT72211, 1024 writes to the SN74ACT72221, 2048 writes to the SN74ACT72231, and 4096 writes to

the SN74ACT72241. Attempted write cycles are ignored when FF is low. FF is set high by the first low-to-high

transition of WCLK after data is read from a full FIFO. FF and PAF are each synchronized to the low-to-high

transition of WCLK by one flip-flop.

If a device is configured to have two write enables (see device reset), data is read by the low-to-high transition

of read clock (RCLK) when both read enables (REN1, REN2) are low and EF is high. WEN2/LD must also be

high if the device is configured to have programmable flags. A read from the FIFO puts RAM data on Q0 – Q8

and increments the read pointer in the same sequence as the write pointer. New data is not shifted to the output

EF and PAE are each synchronized to the low-to-high transition of RCLK by one flip-flop. When the device is

empty, the write and read pointers are equal and EF is set low. Attempted read cycles are ignored while EF is

set low. EF is set high by the first low-to-high transition of RCLK after data is written to an empty FIFO.

WCLK and RCLK can be asynchronous or coincident to one another. Writing data to FIFO memory is

independent of reading data from FIFO memory and vice versa.

flag programming

When WEN2/LD is held low during a device reset (RS = V

), the input is the load (LD) enable for flag offset

programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained

in the SN74ACT72211L / -72221L / -72231L / -72241L for writing or reading data.

When the device is configured for programmable flags and both WEN2/LD and WEN1 are low, the first

low-to-high transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB)

significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD

and WEN1 are low. The fifth low-to-high transition of WCLK while WEN2/LD and WEN1 are low writes data to

the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types.

It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written;

then, by bringing the WEN2/LD input high, the FIFO is returned to normal read and write operation. The next

time WEN2/LD is brought low, a write operation stores data in the next offset register in sequence.

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

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