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Datasheet> All Categories > logic> logic> SN54HC4060J
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SN54HC4060J

Description
Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up Direction, CMOS, CDIP16, 0.300 INCH, CERAMIC, DIP-16
Categorylogic    logic   
File Size190KB，9 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric View All

SN54HC4060J Overview

Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up Direction, CMOS, CDIP16, 0.300 INCH, CERAMIC, DIP-16

SN54HC4060J Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIP,
Reach Compliance Codeunknown
Other featuresOUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT
Counting directionUP
seriesHC/UH
JESD-30 codeR-GDIP-T16
length19.56 mm
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Operating modeASYNCHRONOUS
Number of digits14
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)735 ns
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width7.62 mm
minfmax22 MHz

SN54HC4060J Preview

SN54HC4060, SN74HC4060
14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
SCLS161B – DECEMBER 1982 – REVISED MAY 1997
D
D
Allow Design of Either RC or Crystal
Oscillator Circuits
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HC4060 . . . J OR W PACKAGE
SN74HC4060 . . . D OR N PACKAGE
(TOP VIEW)
description
The ’HC4060 consist of an oscillator section and
14 ripple-carry binary counter stages. The
oscillator configuration allows design of either RC
or crystal-oscillator circuits. A high-to-low
transition on the clock (CLKI) input increments the
counter. A high level at the clear (CLR) input
disables the oscillator (CLKO goes high and
CLKO goes low) and resets the counter to zero (all
Q outputs low).
The SN54HC4060 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC4060 is characterized for
operation from –40°C to 85°C.
Q
L
Q
M
Q
N
Q
F
Q
E
Q
G
Q
D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
J
Q
H
Q
I
CLR
CLKI
CLKO
CLKO
SN54HC4060 . . . FK PACKAGE
(TOP VIEW)
Q
N
Q
F
NC
Q
E
Q
G
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
V
CC
Q
J
Q
H
Q
I
NC
CLR
CLKI
RCTR14
3
7
5
QD
QE
QF
QG
QH
QI
QJ
QL
QM
QN
CLKO
CLKO
NC – No internal connection
1 +
4
6
14
CT
9
13
15
1
2
13
&
3
10
Z1
9
CLR
12
CT=0
11
CLKI
11
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Q
D
GND
NC
CLKO
CLKO
logic symbol
†
Q
M
Q
L
1
SN54HC4060, SN74HC4060
14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
SCLS161B – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
4
QF
6
QG
14
QH
13
QI
15
QJ
1
QL
2
QM
3
QN
CLR
12
R
T
9
CLKO
CLKO
7
QD
5
QE
R
T
R
T
R
T
R
T
CLKI
11
10
Pin numbers shown are for the D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC4060, SN74HC4060
14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
SCLS161B – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HC4060
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
TA
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) time
Operating free-air temperature
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
–55
0.5
1.35
1.8
VCC
VCC
1000
500
400
125
NOM
5
MAX
6
SN74HC4060
MIN
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
–40
0.5
1.35
1.8
VCC
VCC
1000
500
400
85
°C
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
All outputs
VOH
Q outputs
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20
µA
IOL = 4 mA
IOL = 5.2 mA
IO = 0
VI = VIH or VIL
IOH = –20
µA
4.5 V
6V
4.5 V
6V
2V
All outputs
VOL
Q outputs
II
ICC
Ci
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
VI = VIH or VIL
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
SN54HC4060
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC4060
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
nA
µA
pF
V
V
MAX
UNIT
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54HC4060, SN74HC4060
14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
SCLS161B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
fclock
Clock frequency
4.5 V
6V
2V
CLKI high or low
tw
Pulse duration
CLR high
4.5 V
6V
2V
4.5 V
6V
2V
tsu
Setup time, CLR inactive before CLKI↓
↓
4.5 V
6V
TA = 25°C
MIN
MAX
0
0
0
90
18
15
90
18
15
160
32
27
5.5
28
33
SN54HC4060
MIN
0
0
0
135
27
23
135
27
23
240
48
41
MAX
3.7
19
22
SN74HC4060
MIN
0
0
0
115
23
20
115
23
20
200
40
34
ns
ns
MAX
4.3
22
25
MHz
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
fmax
4.5 V
6V
2V
tpd
CLKI
QD
4.5 V
6V
2V
tPHL
CLR
Any Q
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
5.5
28
33
10
45
53
240
58
42
66
18
14
28
8
6
490
98
83
140
28
24
75
15
30
SN54HC4060
MIN
3.7
19
22
735
147
125
210
42
36
110
22
19
MAX
SN74HC4060
MIN
4.3
22
25
615
123
105
175
35
30
95
19
16
ns
ns
ns
MHz
MAX
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load
TYP
88
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC4060, SN74HC4060
14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
SCLS161B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
LOAD CIRCUIT
VCC
50%
tPLH
In-Phase
Output
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
Low-Level
Pulse
50%
Data
Input
50%
10%
Reference
Input
tsu
90%
90%
VCC
50%
10% 0 V
tf
50%
VCC
0V
tr
Input
VOLTAGE WAVEFORMS
SETUP AND INPUT RISE AND FALL TIMES
High-Level
Pulse
VCC
50%
tw
VCC
50%
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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