Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK9515-100A
BUK9615-100A
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
V
GS
= 10 V
MAX.
100
75
230
175
15
14.4
UNIT
V
A
W
˚C
mΩ
mΩ
PINNING
TO220AB & SOT404
PIN
1
2
3
DESCRIPTION
gate
drain
2
PIN CONFIGURATION
mb
tab
SYMBOL
d
g
3
SOT404
1 2 3
source
1
tab/mb drain
TO220AB
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
≤50µS
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
100
100
10
15
75
53
313
230
175
UNIT
V
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
CONDITIONS
-
in free air
Minimum footprint, FR4
board
TYP.
-
60
50
MAX.
0.65
-
-
UNIT
K/W
K/W
K/W
November 1999
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 100 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
V
GS
= 4.5 V; I
D
= 25 A
T
j
= 175˚C
T
j
= 175˚C
MIN.
100
89
1
0.5
-
-
-
-
-
-
-
-
BUK9515-100A
BUK9615-100A
TYP.
-
-
1.5
-
-
0.05
-
2
12
-
11.5
-
MAX.
-
-
2.0
-
2.3
10
500
100
15
40.5
14.4
16
UNIT
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
d
L
s
PARAMETER
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal drain inductance
Internal source inductance
V
DD
= 30 V; R
load
=1.2Ω;
V
GS
= 5 V; R
G
= 10
Ω
CONDITIONS
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
-
-
-
-
-
-
-
-
-
-
-
TYP.
6500
550
325
45
130
400
130
4.5
3.5
2.5
7.5
MAX.
8600
660
400
65
195
560
190
-
-
-
-
UNIT
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
nH
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 75 A; V
GS
= 0 V
I
F
= 75 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.85
1.1
60
0.24
MAX.
75
313
1.2
-
-
-
UNIT
A
A
V
V
ns
µC
November 1999
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 35 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
BUK9515-100A
BUK9615-100A
TYP.
-
MAX.
120
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
RDS(ON) = VDS/ID
100
tp =
1uS
100uS
1mS
10
DC
10mS
100mS
0
20
40
60
80
100
Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth / (K/W)
D=
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
T
P
D
t
p
D=
t
p
T
t
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
1
0
20
40
60
80
100
Tmb / C
120
140
160
180
0.001
0.00001
0.001
t/S
0.1
10
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
November 1999
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9515-100A
BUK9615-100A
250
ID/A
200
VGS/V =
10.0
5.0
100
4.0
3.8
3.6
3.4
ID/A
80
150
3.2
100
3.0
2.8
50
2.6
2.4
0
60
40
Tj/C =
175
25
20
0
2
4
VDS/V
6
8
10
0
0
0.5
1
1.5 VGS/V 2
2.5
3
3.5
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
150
gfs/S
20
19
18
17
100
VGS/V =
16
15
14
13
12
11
0
3.0
3.2
3.4
3.6
4.0
5.0
20
40
60
80
100
50
0
ID/A
0
20
40
ID/A
60
80
100
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
RDS(ON)/mOhm
Fig.9. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Rds(on) normalised to 25degC
15
14.5
14
13.5
3
a
2.5
2
13
12.5
12
11.5
11
10.5
0.5
1
1.5
3
4
5
6
VGS/V
7
8
9
10
-100
-50
0
50
100
Tmb / degC
150
200
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 25 A;
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
November 1999
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9515-100A
BUK9615-100A
2.5
VGS(TO) / V
max.
6
VGS/V
5
2
typ.
1.5
3
4
VDS =
14V
80V
min.
1
2
0.5
1
0
-100
-50
0
50
Tj / C
100
150
200
0
0
10
20
30
40
50
60
70
QG/nC
80
90
100
110
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
100
ID/A
80
1E-01
1E-02
2%
typ
98%
60
Tj/C =
40
175
25
1E-03
1E-04
20
1E-05
0
1E-05
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
0.6 0.7
VSDS/V
0.8
0.9
1
1.1
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
20
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
15
90
80
70
Thousands
10
60
50
Ciss
40
30
20
10
0
20
40
60
80
100
120
Tmb / C
140
160
180
5
0
0.01
0.1
1
VDS/V
10
100
Coss
Crss
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
November 1999
5
Rev 1.000
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