PCF8576D
Universal LCD driver for low multiplex rates
Rev. 13 — 10 May 2012
Product data sheet
1. General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)
1
with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D is compatible with most
microcontrollers and communicates via the two-line bidirectional I
2
C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
•
PCF8576DT/2 should not be used for new design-ins. Replacement part is
PCF85176T/1 for industrial applications
•
PCF8576DT/S400/2 should not be used for new design-ins. Replacement part is
PCA85176T/Q900/1 for automotive applications
2. Features and benefits
AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
Selectable display bias configuration: static,
1
⁄
2
, or
1
⁄
3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
Up to 20 7-segment numeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 elements
40
×
4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 6.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I
2
C-bus interface
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
Section 20.
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
May be cascaded for large LCD applications (up to 2560 elements possible)
No external components required
Compatible with chip-on-glass and chip-on-board technology
Manufactured in silicon gate CMOS process
3. Ordering information
Table 1.
Ordering information
Package
Name
PCF8576DT/2
[1]
PCF8576DT/S400/2
[2]
PCF8576DU/DA/2
PCF8576DU/2DA/2
[1]
[2]
[3]
[4]
Type number
Description
plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
59 bonding pads
[3]
59 bumps
[4]
Version
SOT364-1
SOT364-1
PCF8576DU/DA
PCF8576DU/2DA
TSSOP56
TSSOP56
wire bond die
bare die
Not to be used for new designs. Replacement part is PCF85176T/1 for industrial applications.
Not to be used for new designs. Replacement part is PCA85176T/Q900/1 for automotive applications.
Chips in tray.
Chips with bumps in tray.
4. Marking
Table 2.
Marking codes
Marking code
PCF8576DT
PCF8576DT/S400
PC8576D-2
PC8576D-2
Type number
PCF8576DT/2
PCF8576DT/S400/2
PCF8576DU/DA/2
PCF8576DU/2DA/2
PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 13 — 10 May 2012
2 of 56
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
BP2
BP1
BP3
S0
S1
S2
S3
S4
S5
1
2
3
4
5
6
7
8
9
56 BP0
55 V
LCD
54 V
SS
53 SA0
52 A2
51 A1
50 A0
49 OSC
48 V
DD
47 CLK
46 SYNC
45 SCL
44 SDA
43 S39
42 S38
41 S37
40 S36
39 S35
38 S34
37 S33
36 S32
35 S31
34 S30
33 S29
32 S28
31 S27
30 S26
29 S25
001aaf646
S6 10
S7 11
S8 12
S9 13
S10 14
S11 15
S12 16
S13 17
S14 18
S15 19
S16 20
S17 21
S18 22
S19 23
S20 24
S21 25
S22 26
S23 27
S24 28
PCF8576DT
Top view. For mechanical details, see
Figure 25.
Fig 2.
Pinning diagram for PCF8576DT (TSSOP56)
PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 13 — 10 May 2012
4 of 56
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
35
34
33
32
31
30
29
28
27
26
25
24
23
22
S4
21
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S3
S2
S1
S0
BP3
BP1
BP2
BP0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
20
19
18
17
16
15
14
PCF8576DU
13
V
LCD
12
V
SS
11
10
9
SA0
A2
A1
52
53
54
55
56
57
58
59
1
2
3
4
5
6
7
OSC
CLK
V
DD
S34
S35
S36
S37
S38
S39
C2
SDA
SDA
SDA
SCL
SCL
SYNC
A0
8
C1
001aag424
© NXP B.V. 2012. All rights reserved.
Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see
Figure 26
and
Figure 27.
Fig 3.
Pinning diagram for PCF8576DU (bare die)
PCF8576D
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 13 — 10 May 2012
5 of 56
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