MCM69L737AZP9 datasheet, PDF - EEWORLD Datasheet

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MCM69L737AZP9: DescriptionIC,SYNC SRAM,128KX36,BICMOS,BGA,119PIN,PLASTIC; Categorystorage storage; File Size368KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MCM69L737AZP9 Overview

IC,SYNC SRAM,128KX36,BICMOS,BGA,119PIN,PLASTIC

MCM69L737AZP9 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	9 ns
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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MOTOROLA

Freescale Semiconductor, Inc.

Order this document

by MCM69L737A/D

SEMICONDUCTOR TECHNICAL DATA

Advance Information

4M Late Write LVTTL

MCM69L737A

MCM69L819A

Freescale Semiconductor, Inc...

The MCM69L737A/819A is a 4 megabit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69L819A

organized as 256K words by 18 bits, and the MCM69L737A organized as 128K

words by 36 bits wide are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of

the RAM. At the rising edge of the CK clock all addresses, write enables, and

synchronous selects are registered. An internal buffer and special logic enable

the memory to accept write data on the rising edge of the CK clock a cycle after

address and control signals. Read data is available at the falling edge of the CK

clock.

The RAM uses LVTTL 3.3 V inputs and outputs.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

Byte Write Control

Single 3.3 V + 10%, – 5% Operation

LVTTL 3.3 V I/O (VDDQ)

Asynchronous Output Enable

Compatible

Boundary Scan (JTAG) IEEE

1149.1

Differential Clock Inputs

Optional x18 or x36 organization

MCM69L737A/819A–8.5 = 8.5 ns

MCM69L737A/819A–9 = 9 ns

MCM69L737A/819A–9.5 = 9.5 ns

•

Sleep Mode Operation (ZZ Pin)

•

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

•

ZP PACKAGE

PBGA

CASE 999–01

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

8/15/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM69L737A•MCM69L819A

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