74LVC161D,118 datasheet, PDF - EEWORLD Datasheet

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74LVC161D,118: DescriptionLVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16; Categorylogic logic; File Size162KB，22 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC161D,118 Overview

LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16

74LVC161D,118 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconduc
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOP
package instruction	3.90 MM, PLASTIC, MS-012, SOT-109, SO-16
Contacts	16
Manufacturer packaging code	SOT109-1
Reach Compliance Code	compli
Is Samacsys	N
Other features	TCO OUTPUT
Counting direction	UP
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.9 mm
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Su	120000000 Hz
MaximumI(ol)	0.024 A
Operating mode	SYNCHRONOUS
Humidity sensitivity level	1
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
propagation delay (tpd)	9.5 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	3.9 mm
minfmax	150 MHz
Base Number Matches	1

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74LVC161

Presettable synchronous 4-bit binary counter; asynchronous

reset

Rev. 5 — 23 November 2012

Product data sheet

1. General description

The 74LVC161 is a synchronous presettable binary counter which features an internal

look-ahead carry and can be used for high-speed counting. Synchronous operation is

provided by having all flip-flops clocked simultaneously on the positive-going edge of the

clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level

or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting

action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter

on the positive-going edge of the clock (provided that the set-up and hold time

requirements for PE are met). Preset takes place regardless of the levels at count enable

inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four

outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins

CP, PE, CET and CEP (thus providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs

(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the

terminal count output (pin TC). The TC output thus enabled will produce a HIGH output

pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be

used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by t

PHL

(propagation delay CP to TC) and t

(set-up time CEP to CP) according to the formula:

max

-----------------------------------

PHL



max



It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to

most advanced CMOS compatible TTL families.

2. Features and benefits



5 V tolerant inputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Asynchronous reset

Synchronous counting and loading

Two count enable inputs for n-bit cascading

Positive edge-triggered clock

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)

74LVC161D,118 Related Products

	74LVC161D,118	74LVC161DB,118	74LVC161PW,112	74LVC161BQ,115
Description	LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16	LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16	LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16	LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
Brand Name	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP
Parts packaging code	SOP	SSOP1	TSSOP	QFN
package instruction	3.90 MM, PLASTIC, MS-012, SOT-109, SO-16	SSOP, SSOP16,.3	TSSOP, TSSOP16,.25	HVQCCN, LCC16,.1X.14,20
Contacts	16	16	16	16
Manufacturer packaging code	SOT109-1	SOT338-1	SOT403-1	SOT763-1
Reach Compliance Code	compli	compli	compli	compli
Counting direction	UP	UP	UP	UP
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PQCC-N16
JESD-609 code	e4	e4	e4	e4
length	9.9 mm	6.2 mm	5 mm	3.5 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Load/preset input	YES	YES	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Maximum Frequency@Nom-Su	120000000 Hz	120000000 Hz	120000000 Hz	120000000 Hz
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Humidity sensitivity level	1	1	1	1
Number of digits	4	4	4	4
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SSOP	TSSOP	HVQCCN
Encapsulate equivalent code	SOP16,.25	SSOP16,.3	TSSOP16,.25	LCC16,.1X.14,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TAPE AND REEL	TAPE AND REEL	TUBE	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V
propagation delay (tpd)	9.5 ns	9.5 ns	9.5 ns	9.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	2 mm	1.1 mm	1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	NO LEAD
Terminal pitch	1.27 mm	0.65 mm	0.65 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	30	30	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	3.9 mm	5.3 mm	4.4 mm	2.5 mm
minfmax	150 MHz	150 MHz	150 MHz	150 MHz
Base Number Matches	1	1	1	1
Is Samacsys	N	N	N	-
Other features	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT	-

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