74LVC373APW,118 datasheet, PDF

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74LVC373APW,118: DescriptionLVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20; Categorylogic logic; File Size147KB，19 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC373APW,118 Overview

LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20

74LVC373APW,118 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconduc
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP2
package instruction	TSSOP, TSSOP20,.25
Contacts	20
Manufacturer packaging code	SOT360-1
Reach Compliance Code	compli
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	6.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	8.5 ns
propagation delay (tpd)	10.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
Base Number Matches	1

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74LVC373A

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 3 — 22 November 2012

Product data sheet

1. General description

The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type

inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable

input (pin LE) and an output enable input (pin OE) are common to all internal latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this

condition, the latches are transparent, that is, a latch output will change each time its

corresponding D-input changes. When pin LE is LOW, the latches store the information

that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of

pin LE.

When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins

Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.

Operation of input pin OE does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

The 74LVC373A is functionally identical to the 74LVC573A, but has a different pin

arrangement.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

High-impedance outputs when V

= 0 V

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

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Description	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
Brand Name	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	TSSOP2	QFN	SOP	SOP	SSOP2	SSOP2	TSSOP2
package instruction	TSSOP, TSSOP20,.25	HVQCCN, LCC20,.1X.18,20	7.50 MM, PLASTIC, MS-013, SOT-163-1, SO-20	SOP, SOP20,.4	5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20	SSOP, SSOP20,.3	TSSOP, TSSOP20,.25
Contacts	20	20	20	20	20	20	20
Manufacturer packaging code	SOT360-1	SOT764-1	SOT163-1	SOT163-1	SOT339-1	SOT339-1	SOT360-1
Reach Compliance Code	compli	compli	compli	compli	compli	compli	compli
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G20	R-PQCC-N20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e4	e4	e4	e4	e4	e4	e4
length	6.5 mm	4.5 mm	12.8 mm	12.8 mm	7.2 mm	7.2 mm	6.5 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Humidity sensitivity level	1	1	1	1	1	1	1
Number of digits	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1
Number of ports	2	2	2	2	2	2	2
Number of terminals	20	20	20	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	HVQCCN	SOP	SOP	SSOP	SSOP	TSSOP
Encapsulate equivalent code	TSSOP20,.25	LCC20,.1X.18,20	SOP20,.4	SOP20,.4	SSOP20,.3	SSOP20,.3	TSSOP20,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL	TAPE AND REEL	TUBE	TAPE AND REEL	TUBE	TAPE AND REEL	TUBE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Su	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns
propagation delay (tpd)	10.5 ns	10.5 ns	10.5 ns	10.5 ns	10.5 ns	10.5 ns	10.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1 mm	2.65 mm	2.65 mm	2 mm	2 mm	1.1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	NO LEAD	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.5 mm	1.27 mm	1.27 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	QUAD	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	4.4 mm	2.5 mm	7.5 mm	7.5 mm	5.3 mm	5.3 mm	4.4 mm
Base Number Matches	1	1	1	1	1	1	1

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