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WF512K32N-120G4TM5A

Description
512K X 32 FLASH 5V PROM MODULE, 90 ns, CPGA66
Categorystorage   
File Size165KB,15 Pages
ManufacturerETC
Download Datasheet Parametric View All

WF512K32N-120G4TM5A Overview

512K X 32 FLASH 5V PROM MODULE, 90 ns, CPGA66

WF512K32N-120G4TM5A Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals66
Minimum operating temperature-55 Cel
Maximum operating temperature125 Cel
Rated supply voltage5 V
Minimum supply/operating voltage4.5 V
Maximum supply/operating voltage5.5 V
Processing package description1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
stateTransferred
ypeNOR TYPE
sub_categoryFlash Memories
ccess_time_max90 ns
data_pollingYES
jesd_30_codeS-CPGA-P66
jesd_609_codee0
storage density1.68E7 bi
Memory IC typeFLASH MODULE
Spare memory width16
moisture_sensitivity_levelNOT SPECIFIED
umber_of_sectors_size32
Number of digits524288 words
Number of digits512K
operating modeASYNCHRONOUS
organize512KX32
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
ckage_codePGA
ckage_equivalence_codePGA66,11X11
packaging shapeSQUARE
Package SizeGRID ARRAY
serial parallelPARALLEL
eak_reflow_temperature__cel_NOT SPECIFIED
wer_supplies__v_5
gramming_voltage__v_5
qualification_statusCOMMERCIAL
screening_level38535Q/M;38534H;883B
seated_height_max4.6 mm
sector_size__words_16K
standby_current_max0.0065 Am
Maximum supply voltage0.2400 Am
surface mountNO
CraftsmanshipCMOS
Temperature levelMILITARY
terminal coatingTIN LEAD
Terminal formPIN/PEG
Terminal spacing2.54 mm
Terminal locationPERPENDICULAR
ime_peak_reflow_temperature_max__s_NOT SPECIFIED
ggle_biNO
length27.3 mm
width27.3 mm
dditional_featureUSER CONFIGURABLE AS 2M X 8
WF512K32-XXX5
HI-RELIABILITY PRODUCT
512Kx32 5V FLASH MODULE, SMD 5962-94612
FEATURES
s
Access Times of 60, 70, 90, 120, 150ns
s
Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400
(1)
)
• 68 lead, 40mm, Low Capacitance Hermetic CQFP
(Package 501)
• 68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP
(Package 502)
• 68 lead, 22.4mm (0.880") Low Profile CQFP (G2U), 3.5mm
(0.140") high, (Package 510)
• 68 lead, 23.9mm (0.940") Low Profile CQFP (G1U), 3.5mm
(0.140") high, (Package 519)
s
100,000 Erase/Program Cycles Minimum
s
Sector Architecture
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s
Organized as 512Kx32
s
Commercial, Industrial and Military Temperature Ranges
s
5 Volt Programming. 5V
±
10% Supply.
s
Low Power CMOS, 6.5mA Standby
s
Embedded Erase and Program Algorithms
s
TTL Compatible Inputs and CMOS Outputs
s
Built-in Decoupling Caps for Low Noise Operation
s
Page Program Operation and Internal Program Control Time
s
Weight
WF512K32-XG2UX5 - 8 grams typical
WF512K32-XH1X5 - 13 grams typical
WF512K32-XG4X5 - 20 grams typical
WF512K32-XG4TX5 - 20 grams typical
WF512K32-XG1UX5 - 5 grams typical
1. Call factory for PGA type (HIP) package options.
Note: See Flash Programming Application Note 4M5 for algorithms.
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WF512K32N-XH1X5
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
17
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
NC
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
4
A
5
A
6
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
8
8
8
8
PIN DESCRIPTION
56
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
W E
1
CS
1
OE
A
0
-
18
512K x 8
512K x 8
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
512K x 8
512K x 8
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
April 2001 Rev. 4
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
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