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Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> FIN1532MX
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FIN1532MX

Description
QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size928KB，7 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Environmental Compliance  
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FIN1532MX Overview

QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16

FIN1532MX Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerRochester Electronics
Parts packaging codeSOIC
package instruction0.150 INCH, MS-012, SOIC-16
Contacts16
Reach Compliance Codeunknown
Input propertiesDIFFERENTIAL
Interface integrated circuit typeLINE RECEIVER
Interface standardsEIA-644; TIA-644
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Humidity sensitivity level1
Number of functions4
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Certification statusCOMMERCIAL
Maximum receive delay3 ns
Number of receiver bits4
Maximum seat height1.75 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm

FIN1532MX Preview

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FIN1532 5V LVDS 4-Bit High Speed Differential Receiver
December 2001
Revised December 2001
FIN1532
5V LVDS 4-Bit High Speed Differential Receiver
General Description
This quad receiver is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typ-
ical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipa-
tion even at high frequencies. This device is ideal for high
speed transfer of clock and data.
The FIN1532 can be paired with its companion driver, the
FIN1531, or any other LVDS driver.
Features
s
Greater than 400Mbs data rate
s
5V power supply operation
s
0.5 ns maximum differential pulse skew
s
3 ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection for inputs and outputs
s
Fail safe protection for open-circuit, shorted and termi-
nated receiver inputs
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Pin compatible with equivalent RS-422
and PECL devices
s
16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1532M
FIN1532MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Name
R
IN1+
, R
IN2+
, R
IN3+
, R
IN4+
R
IN1−
, R
IN2−
, R
IN3−
, R
IN4−
EN
EN
V
CC
GND
Description
Non-inverting LVDS Inputs
Inverting LVDS Inputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
R
OUT1
, R
OUT2
, R
OUT3
, R
OUT4
LVTTL Data Outputs
Connection Diagram
Function Table
Input
EN
H
H
H
X
X
X
L
H
=
HIGH Logic Level
Z
=
High Impedance
Outputs
R
IN+
H
L
H
L
X
R
IN+
L
H
L
H
R
OUT
H
L
H
H
L
H
Z
Top View
EN
X
X
X
L
L
L
H
Fail Safe Condition
Fail Safe Condition
L
=
LOW Logic Level
X
=
Don’t Care
Fail Safe
=
Open, Shorted, Terminated
© 2001 Fairchild Semiconductor Corporation
DS500504
www.fairchildsemi.com
FIN1532
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
Enable Inputs
Receiver Inputs
DC Output Voltage (V
OUT
)
DC Output Current (I
O
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
−
0.5 V to
+
6 V
−
0.5 V to
+
6 V
−
0.5 V to
+
6 V
−
0.5 V to
+
6 V
16 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Enable Inputs
Receiver Inputs
Magnitude of Differential Voltage
(|V
ID
|)
Common-mode Input Voltage
(V
IC
)
Operating Temperature (T
A
)
|V
ID
|/2 to (2.4
−
|V
ID
|/2)
100 mV to 600 mV
0 to V
CC
0 to 2.4 V
4.5 V to 5.5 V
−
65
°
C to
+
150
°
C
150
°
C
−
40
°
C to
+
85
°
C
≥
8000 V
≥
300 V
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
TH
V
TL
I
IN
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current EN or EN
Input Current Receiver Inputs
V
IH
V
IL
V
OH
V
OL
V
IK
I
OZ
I
O(OFF)
I
OS
I
CCZ
I
CC
I
PU/PD
C
IN
C
OUT
Input High Voltage (EN or EN)
Input Low Voltage (EN or EN)
Output HIGH Voltage
Output LOW Voltage
Input Clamp Voltage
Disabled Output Leakage Current
Power-OFF Output Current
Output Short Circuit Test
Disabled Power Supply Current
Power Supply Current
Output Power Up/Power Down
High Z Leakage Current
Input Capacitance
Output Capacitance
5.5
4.5
pF
pF
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
=
100
µA
I
OL
=
8 mA
I
IK
= −18
mA
EN
=
0.8 and EN
=
2V, V
OUT
=
5.5V or 0V
V
OUT
=
0V or 5.5V, V
CC
=
0V
Receiver Enabled, V
OUT
=
0V
(one output shorted at a time)
Receiver Disabled
Receiver Enabled, R
IN
+
=
1V and R
IN
−
=
1.4V
Receiver Enabled, R
IN
+
=
1.4V and R
IN
−
=
1V
V
CC
=
0V to 2.0V
−15
1.2
11
15
−1.5
Test Conditions
V
IC
= +1.2V,
See Figure 1
V
IC
= +1.2V,
See Figure 1
V
IN
=
0V or V
CC
, V
CC
=
5.5 or 0V
V
IN
=
0V or 2.4 V, V
CC
=
5.5 or 0V
2.0
GND
V
CC
−0.2
3.8
4.98
4.68
0.01
0.22
−0.8
±20
50
−100
5
17
23
±20
0.2
0.5
−100
±20
±20
V
CC
0.8
Min
Typ
(Note 2)
100
Max
Units
mV
mV
µA
µA
V
V
V
V
V
µA
µA
mA
mA
mA
µA
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
5V.
www.fairchildsemi.com
2
FIN1532
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
ZH
t
ZL
t
HZ
t
LZ
Parameter
Propagation Delay
LOW-to-HIGH
Propagation Delay
HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
(Note 6)
R
L
=
1kΩ, C
L
=
10 pF,
See Figure 1 and Figure 2
200
260
8
8
4
4
12.0
12.0
8.0
8.0
|V
ID
|
=
400 mV, C
L
=
10 pF, R
L
=
1kΩ
See Figure 1 and Figure 2
Test Conditions
Min
Typ
(Note 3)
1.0
1.0
2.0
2.0
1.3
1.1
0.2
0.1
0.5
0.3
1.0
3.0
3.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
LVTTL Output Enable Time from Z to HIGH R
L
=
1kΩ, C
L
=
10 pF,
LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
5V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
=
t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Note A:
All input pulses have frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay
3
www.fairchildsemi.com
FIN1532
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
FIGURE 3. AC Loading Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
Note A:
C
L
includes probes and jig capacitance
Note B:
All LVTTL input pulses have the following characteristics: Frequency
=
10 MHz, t
R
or t
F
=
2 ns
FIGURE 4. LVTTL Outputs Test Circuit and AC Waveforms
www.fairchildsemi.com
4
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FIN1532MX Related Products

FIN1532MX FIN1532MTCX FIN1532MTC FIN1532M
Description QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16 QUAD LINE RECEIVER, PDSO16, 4.40 MM, MO-153, TSSOP-16 QUAD LINE RECEIVER, PDSO16, 4.40 MM, MO-153, TSSOP-16 QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16
Is it lead-free? Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
Parts packaging code SOIC TSSOP TSSOP SOIC
package instruction 0.150 INCH, MS-012, SOIC-16 4.40 MM, MO-153, TSSOP-16 4.40 MM, MO-153, TSSOP-16 0.150 INCH, MS-012, SOIC-16
Contacts 16 16 16 16
Reach Compliance Code unknown unknown unknown unknown
Input properties DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
Interface integrated circuit type LINE RECEIVER LINE RECEIVER LINE RECEIVER LINE RECEIVER
Interface standards EIA-644; TIA-644 EIA-644; TIA-644 EIA-644; TIA-644 EIA-644; TIA-644
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e4 e4 e3
length 9.9 mm 5 mm 5 mm 9.9 mm
Humidity sensitivity level 1 1 1 1
Number of functions 4 4 4 4
Number of terminals 16 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP TSSOP TSSOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 260 260 260
Certification status COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Maximum receive delay 3 ns 3 ns 3 ns 3 ns
Number of receiver bits 4 4 4 4
Maximum seat height 1.75 mm 1.2 mm 1.2 mm 1.75 mm
Maximum supply voltage 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface MATTE TIN NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD MATTE TIN
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm 0.65 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 NOT SPECIFIED NOT SPECIFIED
width 3.9 mm 4.4 mm 4.4 mm 3.9 mm

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