CMOS 16-BIT SINGLE CHIP MICROCOMPUTER
S1C17701
TECHNICAL MANUAL
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission
of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not
assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or
use in any product or circuit and, further, there is no representation that this material is applicable to products requir-
ing high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by
implication or otherwise, and there is no representation or warranty that anything made in accordance with this mate-
rial will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain
technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade
Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval
from another government agency.
This product uses SuperFlash
®
technology licensed from Silicon Storage Technology, Inc.
©
SEIKO EPSON CORPORATION
2008, All rights reserved.
S1C17701 Technical Manual Revision History
Code No.
411089901
Page
1-1
Chapter/Section
1 Overview
1-2
1.1 Features
Contents
Table 1.1 deleted.
Description added.
Main (OSC3) oscillator
• Crystal/ceramic oscillator 8.2 MHz (max.)
• CR oscillator 2.2 MHz (max.)
Part numbers deleted.
Main (OSC3) oscillator
(• S1C17701F00B100)
(• S1C17701F00E100)
1-4
1.3.1 Pin Arrangement
Descriptions modified.
Shipping form
Part number for plastic package modified.
Descriptions added.
• VFBGA7H-161 package
(7 mm 7 mm 1.0 mm, ball pitch: 0.5 mm)
• VFBGA10H-144 package
(10 mm 10 mm 1.0 mm, ball pitch: 0.8 mm)
Part number added.
TQFP24-144-pin
Figure 1.3.1.1
Part number modified.
QFP24-144pin→TQFP24-144-pin
Figure 1.3.1.2 added.
Figure 1.3.1.3 added.
Table 1.3.2.1 modified.
Descriptions added.
∗
1: SEG17 to SEG55(VFBGA7)...C6, D6, E6, A5,
B5, C5, A4, D5, E5, C4, B4, A3, D4, B3, A2, C3, B2
Description deleted.
(The interrupts can be used to clear standby mode even if
the corresponding interrupt enable bit is set to disable
interrupt.)
Description modified.
The PxIN[7:0] bits correspond to the Px[7:0] ports respectively
and the voltage level on the port pin is read out in the input
mode...In the output mode, an indefinite value is read out.
Numerical value modified.
Expression for I
2
C
Description deleted.
(see Table 22.3.1.)
Table 22.6.1.1 modified.
Description modified.
DSPC[1:0] is reset to 0x0 (display off) after initial
resetting...since switching to SLEEP mode with the
LCD display left on will degrade the LCD.
Table modified.
Description for 0x50a0: LCD Display Control
Register (LCD_DCTL)
Table 22.8.2 modified.
Description modified.
DSPC[1:0] is reset to 0x0 (display off) after initial
resetting...since switching to SLEEP mode with the
LCD display left on will degrade the LCD.
Table modified.
Table modified.
Part number modified.
QFP24-144pin package→TQFP24-144-pin package
Figure added.
VFBGA7H-161 Package
Figure added.
VFBGA10H-144 Package
Table modified.
Coordinates modified.
Table for 0x50a00x50a6 modified.
Description for Noise-Induced Erratic Operations modified.
Index added.
Table 3.2.4.1 modified.
1-5
1-6
1-7
1-8
1.3.2 Pin Description
6-15
6.7 Details of Control Registers
10-11
10.8 Details of Control Registers
11-9
22-3
22-9
11.7 16-bit Timer Output Signal
22.3.2 Frame Signal
22.6.1 Turning Display On and Off
22-14
22.8 Details of Control Registers
22-15
26-5
26-7
27-1
27-2
27-3
28-2
AP-18
AP-36
411089902
3-4
26.5 Current
26.6.3 External Clock Input AC
Characteristics
27 Package
28.2 Pad Coordinates
Appendix A List of I/O Registers
Appendix D Precautions on Mounting
Index
3.2.4 Access Control for the Flash
Controller
Configuration of product number
Devices
S1
C
17xxx
F
00E1
00
Packing specifications
00 : Besides tape & reel
0A : TCP BL
2 directions
0B : Tape & reel BACK
0C : TCP BR
2 directions
0D : TCP BT
2 directions
0E : TCP BD
2 directions
0F : Tape & reel FRONT
0G : TCP BT
4 directions
0H : TCP BD
4 directions
0J : TCP SL
2 directions
0K : TCP SR
2 directions
0L : Tape & reel LEFT
0M: TCP ST
2 directions
0N : TCP SD
2 directions
0P : TCP ST
4 directions
0Q : TCP SD
4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1
C
17000
H2
1
00
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx : Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
S1C17701 Technical Manual
1 Overview
2 CPU
3 Memory Map, Bus Control
4 Power Supply
5 Initial Reset
6 Interrupt Controller (ITC)
7 Oscillator (OSC)
8 Clock Generator (CLG)
9 Prescaler (PSC)
10 I/O Ports (P)
11 16-bit Timers (T16)
12 8-bit Timer (T8F)
13 PWM & Capture Timer (T16E)
14 8-bit OSC1 Timer (T8OSC1)
15 Clock Timer (CT)
16 Stopwatch Timer (SWT)
17 Watchdog Timer (WDT)
18 UART
19 SPI
20 I
2
C
21 Remote Controller (REMC)
22 LCD Driver (LCD)
23 Supply Voltage Detector (SVD)
24 On-chip Debugger (DBG)
25 Basic External Wiring Diagram
26 Electrical Characteristics
27 Package
28 Pad Layout
Overview
CPU
Map
Power
Reset
ITC
OSC
CLG
PSC
IOPort
T16
T8F
T16E
T8OSC1
CT
SWT
WDT
UART
SPI
I
2
C
REMC
LCD
SVD
DBG
BEWD
EC
Pack
PadLO
Appendix
A List of I/O Registers
B Flash Programming
C Power Saving
D Precautions on Mounting
E Initialize Routine
AP
IORegs
Flash
PwrSav
Precaut
Init
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