34
TSPC750A/740A
Power
PC750A/740A RISC MICROPROCESSOR
Family
Pid8t–750A/740A Specification
.
DESCRIPTION
The TSPC750A and TSPC740A microprocessor (after named
750A/740A) are low–power implementations of the PowerPC
Reduced Instruction Set Computer (RISC) architecture.
The 750A/740A microprocessors designs are superscalar,
capable of issuing three instructions per clock cycle into six
independent execution units
The 740A/750A microprocessors uses a 2,6/3,3–volts CMOS
process technology and maintains full interface compatibility
with TTL devices.
The 750A/740A provides four software controlable power–
saving modes and a thermal assist unit management.
G suffix
The 750A/740A microprocessors have separate 32–Kbyte,
physically–addressed instruction and data caches and differ
only in that the 750A features a dedicated L2 cache interface
with on–chip L2 tags.
Both are software and bus–compatible with the PowerPC603
and PowerPC604 families, and are fully JTAG compliant.
The TSPC740A microprocessor is pin compatible with the
TSPC603e family.
CBGA255 and CBGA360
Ceramic Ball Grid Array
MAIN FEATURES
H
12.4SPECint95,8.4SPECfp95 @266Mhz (TSPC750A)
w/1MB L2 @133Mhz
H
11.5SPECint95,6.9SPECfp95 @266Mhz (TSPC740A)
H
488 MIPS @ 266Mhz
H
Selectable bus clock (11 CPU bus dividers up to 8x)
H
P
D
typical 4,2W @ 200Mhz, full operating conditions.
H
Nap, doze and sleep modes for power savings
H
Superscalar (3 instructions per clock cycle)
H
4G–Byte direct addressing range.
H
64–bit data and 32–bit address bus interface.
H
32KB instruction and data cache.
H
Six independent execution units and two register files.
H
Write–back and write–through operations.
H
f
int
max = 266Mhz
H
f
bus
max = 83,3Mhz
H
Compatible CMOS input / TTL output
GS suffix
CI–CGA255 and CI–CGA360
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
SCREENING
This product is manufactured in full compliance wtih :
HCBGA
upscreenings based upon TCS standards
HFull
military temperature range (Tc=–55
o
C,+125
o
C)
industrial temperature range (Tc=–40
o
C,+110
o
C)
HCI–CGA
versions of TSPC740A and TSPC750A (planned)
HCI–CGA
packages : MIL–STD–883 class Q or according to
TCS standards (planned)
March 2000
1/42
TSPC750A/740A
SUMMARY
A.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1. General parameters3
1.2. Features
4
2. PIN ASSIGNEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1. TSPC740A package
6
2.2. TSPC750A package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3. PINOUT LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1. Pinout listing for the TSPC740A, 255 CBGA package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2. Pinout listing for the TSPC750A, 360 CBGA package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4. Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
B.
DETAILED SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2. Design and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4. Recommendated operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5. Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2. Thermal management assitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3. Thermal Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6. Power consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1. Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1. Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1. Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2. 60x Bus Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3. 60x Bus Output AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4. L2 Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5. L2 Bus Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6. L2 Bus Output AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1. Parameters for the TSPC740A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1. Mechanical Dimensions of TSPC740A CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2. Mechanical Dimensions of TSPC740A CI–CGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2. Parameters for the TSPC750A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1. Mechanical Dimensions of TSPC750A CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2. Mechanical Dimensions of TSPC750A CI–CGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. SYSTEM DESIGN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2. DecouplingRecommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3. ConnectionRecommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4. Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5. Pull–up Resistor Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
14
14
15
15
15
16
16
19
19
20
21
21
21
22
23
24
26
28
28
31
31
31
31
32
32
32
33
34
34
35
35
38
38
38
38
38
39
40
41
2/42
TSPC750A/740A
A. GENERAL DESCRIPTION
1. SIMPLIFIED BLOCK DIAGRAM
The TSPC750A is targeted for low power systems and supports the following power management features—doze, nap, sleep, and
dynamic power management. The TSPC750A consists of a processor core and an internal L2 Tag combined with a dedicated L2
cache interface and a 60x bus.
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
System Unit
Dispatch
BHT/BTIC
GPRs
FXU1
FXU2
Rename
Buffers
LSU
FPRs
Rename
Buffers
FPU
32K DCache
L2 Tags
L2 Cache
BIU
60x BIU
Figure 1. TSPC750A Block Diagram
1.1.
General parameters
The general parameters of the 750A/740A are the following :
Technology
Die size
Logic design
Packages
L2
0.29 mm CMOS, five–layer metal
7.56 mm x 8.79 mm (67 mm
2
)
6.35 million
Fully–static
740A: Surface mount 255 ceramic ball grid array (CBGA) and column interposer ceramic grid array CI–CGA without
interface
750A: Surface mount 360 ceramic ball grid array (CBGA) and column interposer ceramic grid aray CI–CGA with L2
interface
2.6V
"100
mV
3.3V
"5%
V dc
Transistor count
Core power supply
I/O power supply
3/42
TSPC750A/740A
1.2.
Features
Exept L2 cache interface that is not supported by the PowerPC version, the major features implementated in the PowerPC750A archi-
tecture are as follow:
•
Level 2 (L2) cache interface (not implemented on TSPC740A)
— Internal L2 cache controller and 4K–entry
tags; external data SRAMs
— 256K, 512K, and 1 Mbyte 2–way set
associative L2 cache support
— 64–byte (256K/512K) and 128–byte
(1–Mbyte) sectored line size
— Supports flow–through (reg–buf)
synchronous burst SRAMs, pipelined
(reg–reg) synchronous burst SRAMs, and
— Copy–back or write–through data cache
pipelined (reg–reg) late–write
(on a page basis, or for all L2)
synchronous burst SRAMs
— Core–to–L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5,
and
÷3
supported
•
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512–entry branch history table (BHT) for dynamic prediction
— 64–entry, 4–way set associative branch target instruction cache (BTIC) to minimize branch delay slots
•
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed–point unit 1,
fixed–point unit 2, or floating–point)
— Serialization control (predispatch, postdispatch, execution serialization)
•
Load/store unit
— One cycle load or store cache access (byte, half–word, word, double–word)
— Effective address generation
— Hits under misses (one outstanding miss)
— Single–cycle misaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating–point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big– and little–endian byte addressing supported
— Misaligned little–endian support in hardware
•
Fixed–point units
— Fixed–point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed–point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single–cycle arithmetic, shift, rotate, logical
— Multiply and divide support (multi–cycle)
— Early out multiply
4/42
TSPC750A/740A
•
Bus interface
— Compatible with 60x processor interface
— 32–bit address bus
— 64–bit data bus
— Bus–to–core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x , 8x supported
•
Decode
— Register file access
— Forwarding control
— Partial instruction decode
•
Floating–point unit
— Support for IEEE–754 standard single– and double–precision floating–point arithmetic
— 3 cycle latency, 1 cycle throughput, single–precision multiply–add
— 3 cycle latency, 1 cycle throughput, double–precision add
— 4 cycle latency, 2 cycle throughput, double–precision multiply–add
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non–IEEE mode
•
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
•
Cache structure
— 32K, 32–byte line, 8–way set associative instruction cache
— 32K, 32–byte line, 8–way set associative data cache
— Single–cycle cache access
— Pseudo–LRU replacement
— Copy–back or write–through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non–blocking instruction and data cache (one outstanding miss under hits)
— No snooping of instruction cache
•
Memory management unit
— 128 entry, 2–way set associative instruction TLB
— 128 entry, 2–way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (2
52
) of virtual memory
— Real memory support for up to 4 gigabytes (2
32
) of physical memory
•
Testability
— LSSD scan design
— JTAG interface
5/42
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
